#include "at91sam7s256.h"
#include <intrinsics.h>
//------------------------------------------------------------------------------
#define Main_Oscillator 10000000 // 10.000 MHz
#define UART_CLOCK_9600 16 // 2500000/(9600x16)
#define UART_CONVERTER_TURN_ON (1<<15) // PA15
//------------------------------------------------------------------------------
volatile unsigned int i = 0;
volatile unsigned int RX_FLAG = 0;
//------------------------------------------------------------------------------
void LowLevelInit (void); // runs once at startup
void defaultSpuriousHandler (void) {return;};
void defaultFiqHandler (void) {return;};
void defaultIrqHandler (void) {return;};
void init_COM1 (void);
void init_IRQ (void);
//------------------------------------------------------------------------------
void Usart1IrqHandler (void);
//------------------------------------------------------------------------------
int main (void) {
init_COM1 ();
init_IRQ ();
AT91C_BASE_PIOA->PIO_SODR = UART_CONVERTER_TURN_ON; // Enable MAX3237 conveter
__enable_interrupt();
for (;;) {
while (!(AT91C_BASE_US1->US_CSR & AT91C_US_TXRDY)==1);
AT91C_BASE_US1->US_THR = AT91C_BASE_US1->US_RHR; // simple RX1 -> TX1 works fine!
for (i = 0; i < 10000; i++) {
asm ("nop"); // simple NoOPeration instruction
}
if (RX_FLAG) {
RX_FLAG = 0;
while (!(AT91C_BASE_US1->US_CSR & AT91C_US_TXRDY)==1);
AT91C_BASE_US1->US_THR = 'Y';
}
}
}
//------------------------------------------------------------------------------
void LowLevelInit (void) {
unsigned char i;
unsigned int tmp = 0;
AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; // Watchdog disable
AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(22<<16)) | AT91C_MC_FWS_0FWS; // Set Flash Wait sate: 0 wait states
AT91C_BASE_PMC->PMC_MOR = (AT91C_CKGR_OSCOUNT & (0x40 << 8)) | AT91C_CKGR_MOSCEN; // Initialize Main_Oscillator
while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
tmp = AT91C_BASE_PMC->PMC_MCKR; // Switch Master Clock (MCK) to Main_Oscillator
tmp &= ~AT91C_PMC_CSS;
tmp |= AT91C_PMC_CSS_MAIN_CLK;
AT91C_BASE_PMC->PMC_MCKR = tmp;
while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); // clock debounce
tmp = AT91C_BASE_PMC->PMC_MCKR; // set PRESCALER
tmp &= ~AT91C_PMC_PRES;
tmp |= AT91C_PMC_PRES_CLK_4; // divisor of main clock is 4
AT91C_BASE_PMC->PMC_MCKR = tmp;
while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); // clock debounce
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; // Initialize AIC
AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler; // map default interrupt handlers
for (i = 1; i < 31; i++) AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler; // map default interrupt handlers
AT91C_BASE_AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler; // map default interrupt handlers
for (i = 0; i < 8; i++) AT91C_BASE_AIC->AIC_EOICR = 0; // Unstack nested interrupts
AT91C_BASE_AIC->AIC_DCR = AT91C_AIC_DCR_PROT; // Enable Debug mode
AT91C_BASE_MC->MC_RCR = AT91C_MC_RCB; // Remap the internal SRAM at 0x0
AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN); // Disable RTT and PIT interrupts
AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
AT91C_BASE_PMC->PMC_PCER = (1UL<<AT91C_ID_UDP); // Disable the USB Transceiver, DDM è DDP conneted to GND
AT91C_BASE_UDP->UDP_TXVC = AT91C_UDP_TXVDIS;
AT91C_BASE_PMC->PMC_PCDR = (1UL<<AT91C_ID_UDP); // disable USB clock
AT91C_BASE_ADC->ADC_MR = AT91C_ADC_SLEEP_MODE; // Analog-to-Digital Converter de-activated
}
//------------------------------------------------------------------------------
void init_COM1 (void) {
AT91C_BASE_PMC->PMC_PCER = (1UL<<AT91C_ID_PIOA); // Enable the PIO clock
AT91C_BASE_PIOA->PIO_IDR = UART_CONVERTER_TURN_ON; // Pin Interrupt Disable Register PA15
AT91C_BASE_PIOA->PIO_PER = UART_CONVERTER_TURN_ON; // PIO Enable Register
AT91C_BASE_PIOA->PIO_PPUDR = UART_CONVERTER_TURN_ON; // Pull-Up Disable Resistor
AT91C_BASE_PIOA->PIO_CODR = UART_CONVERTER_TURN_ON; // clear Output Data Register
AT91C_BASE_PIOA->PIO_OER = UART_CONVERTER_TURN_ON; // Output Enable Register
AT91C_BASE_PIOA->PIO_PDR = (1UL<<21) | (1UL<<22); // Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin)
AT91C_BASE_PIOA->PIO_ASR = (1UL<<21) | (1UL<<22); // Assigns the I/O line to the Peripheral A function PA21 and PA22
AT91C_BASE_PIOA->PIO_BSR = 0; // Assigns the I/O line to the Peripheral B function
AT91C_BASE_PMC->PMC_PCER = (1UL<<AT91C_ID_US1); //enable the clock of UART
AT91C_BASE_US1->US_RTOR = 0; // receiver time-out (disabled)
AT91C_BASE_US1->US_TTGR = 0; // transmitter timeguard (disabled)
AT91C_BASE_US1->US_BRGR = UART_CLOCK_9600; // set baud rate divisor register EXT_CLOCK_DIV/9600x16
AT91C_BASE_US1->US_MR = AT91C_US_USMODE_NORMAL | // Normal Mode
AT91C_US_CLKS_CLOCK | // Clock = MCK
AT91C_US_CHRL_8_BITS | // 8-bit Data
AT91C_US_PAR_NONE | // No Parity
AT91C_US_NBSTOP_1_BIT; // 1 Stop Bit
}
//------------------------------------------------------------------------------
void init_IRQ (void) {
AT91C_BASE_AIC->AIC_IDCR = (1<<AT91C_ID_US1); // Disable USART1 interrupt in AIC
AT91C_BASE_US1->US_CR = AT91C_US_RSTRX | // reset receiver
AT91C_US_RSTTX | // reset transmitter
AT91C_US_RXDIS | // disable receiver
AT91C_US_TXDIS; // disable transmitter
AT91C_BASE_US1->US_IER = 0x00; // no usart1 interrupts enabled (no effect)
AT91C_BASE_US1->US_IDR = 0xFFFF; // disable all USART1 interrupts
AT91C_BASE_AIC->AIC_SVR [AT91C_ID_US1] = (unsigned int) Usart1IrqHandler;
AT91C_BASE_AIC->AIC_SMR [AT91C_ID_US1] = (AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL | 0x4 ); // priority (4) in AIC Source Mode Reg
// Clear the interrupt on the interrupt controller
AT91C_BASE_AIC->AIC_ICCR = (1UL<<AT91C_ID_US1);
AT91C_BASE_AIC->AIC_IECR = (1UL<<AT91C_ID_US1);
// enable the USART1 receive interrupt
AT91C_BASE_US1->US_IER = AT91C_US_RXRDY; // enable RXRDY usart1 receive interrupt
AT91C_BASE_US1->US_IDR = ~AT91C_US_RXRDY; // disable all interrupts except RXRDY
// enable the USART1 receiver and transmitter
AT91C_BASE_US1->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
}
//------------------------------------------------------------------------------
void Usart1IrqHandler (void) {
if ((AT91C_BASE_US1->US_CSR & AT91C_US_RXRDY) == AT91C_US_RXRDY) { // we have a receive interrupt
RX_FLAG = 1;
}
}
//------------------------------------------------------------------------------

MODULE ?cstartup

;; Forward declaration of sections.
SECTION IRQ_STACK:DATA:NOROOT(2)
SECTION CSTACK:DATA:NOROOT(3)

//------------------------------------------------------------------------------
// Headers
//------------------------------------------------------------------------------

#define __ASSEMBLY__
#include "at91sam7s256.h"

//------------------------------------------------------------------------------
// Definitions
//------------------------------------------------------------------------------

#define ARM_MODE_ABT 0x17
#define ARM_MODE_FIQ 0x11
#define ARM_MODE_IRQ 0x12
#define ARM_MODE_SVC 0x13
#define ARM_MODE_SYS 0x1F

#define I_BIT 0x80
#define F_BIT 0x40

//------------------------------------------------------------------------------
// Startup routine
//------------------------------------------------------------------------------

/*
Exception vectors
*/
SECTION .vectors:CODE:NOROOT(2)

PUBLIC resetVector
PUBLIC irqHandler

EXTERN Undefined_Handler
EXTERN SWI_Handler
EXTERN Prefetch_Handler
EXTERN Abort_Handler
EXTERN FIQ_Handler

ARM

__iar_init$$done: ; The interrupt vector is not needed
; until after copy initialization is done

resetVector:
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR pc, =resetHandler ; Reset
LDR pc, Undefined_Addr ; Undefined instructions
LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
LDR pc, Prefetch_Addr ; Prefetch abort
LDR pc, Abort_Addr ; Data abort
B . ; RESERVED
LDR pc, =irqHandler ; IRQ
LDR pc, FIQ_Addr ; FIQ

Undefined_Addr: DCD Undefined_Handler
SWI_Addr: DCD SWI_Handler
Prefetch_Addr: DCD Prefetch_Handler
Abort_Addr: DCD Abort_Handler
FIQ_Addr: DCD FIQ_Handler

/*
Handles incoming interrupt requests by branching to the corresponding
handler, as defined in the AIC. Supports interrupt nesting.
*/
irqHandler:
/* Save interrupt context on the stack to allow nesting */
SUB lr, lr, #4
STMFD sp!, {lr}
MRS lr, SPSR
STMFD sp!, {r0, lr}

/* Write in the IVR to support Protect Mode */
LDR lr, =AT91C_BASE_AIC
LDR r0, [r14, #AIC_IVR]
STR lr, [r14, #AIC_IVR]

/* Branch to interrupt handler in Supervisor mode */
MSR CPSR_c, #ARM_MODE_SYS
STMFD sp!, {r1-r3, r4, r12, lr}
MOV lr, pc
BX r0
LDMIA sp!, {r1-r3, r4, r12, lr}
MSR CPSR_c, #ARM_MODE_IRQ | I_BIT

/* Acknowledge interrupt */
LDR lr, =AT91C_BASE_AIC
STR lr, [r14, #AIC_EOICR]

/* Restore interrupt context and branch back to calling code */
LDMIA sp!, {r0, lr}
MSR SPSR_cxsf, lr
LDMIA sp!, {pc}^


/*
After a reset, execution starts here, the mode is ARM, supervisor
with interrupts disabled.
Initializes the chip and branches to the main() function.
*/
SECTION .cstartup:CODE:NOROOT(2)

PUBLIC resetHandler
EXTERN LowLevelInit
EXTERN ?main
REQUIRE resetVector
ARM

resetHandler:

/* Set pc to actual code location (i.e. not in remap zone) */
LDR pc, =label

/* Perform low-level initialization of the chip using LowLevelInit() */
label:
LDR r0, =LowLevelInit
LDR r4, =SFE(CSTACK)
MOV sp, r4
MOV lr, pc
BX r0

/* Set up the interrupt stack pointer. */
MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode
LDR sp, =SFE(IRQ_STACK)

/* Set up the SYS stack pointer. */
MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode
LDR sp, =SFE(CSTACK)

/* Branch to main() */
LDR r0, =?main
MOV lr, pc
BX r0

/* Loop indefinitely when program is finished */
loop4:
B loop4

END[/code]

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Memory Regions-*/
define symbol __ICFEDIT_region_RAM_start__ = 0x200000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_vectors__ = 0x100;
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_sysstack__ = 0x60;
define symbol __ICFEDIT_size_irqstack__ = 0x60;
define symbol __ICFEDIT_size_heap__ = 0x0;
/*-Exports-*/
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;
export symbol __ICFEDIT_size_vectors__;
export symbol __ICFEDIT_size_cstack__;
export symbol __ICFEDIT_size_sysstack__;
export symbol __ICFEDIT_size_irqstack__;
export symbol __ICFEDIT_size_heap__;
/**** End of ICF editor section. ###ICF###*/

define memory mem with size = 4G;
define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];

define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };

do not initialize { section .noinit };

place in VEC_region { section .vectors };
place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP };