Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 10.1 Build 153 11/29/2010 SJ Full Version
    Info: Processing started: Mon Jan 10 21:06:17 2011
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test1 -c test1
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Found 1 design units, including 1 entities, in source file test1.bdf
    Info: Found entity 1: test1
Info: Elaborating entity "test1" for the top level hierarchy
Info: Implemented 3 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 1 output pins
    Info: Implemented 1 macrocells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 201 megabytes
    Info: Processing ended: Mon Jan 10 21:06:19 2011
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 10.1 Build 153 11/29/2010 SJ Full Version
    Info: Processing started: Mon Jan 10 21:06:20 2011
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off test1 -c test1
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Selected device EPM7064SLC44-10 for design "test1"
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 205 megabytes
    Info: Processing ended: Mon Jan 10 21:06:21 2011
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00
Info: *******************************************************************
Info: Running Quartus II Assembler
    Info: Version 10.1 Build 153 11/29/2010 SJ Full Version
    Info: Processing started: Mon Jan 10 21:06:23 2011
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off test1 -c test1
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 186 megabytes
    Info: Processing ended: Mon Jan 10 21:06:24 2011
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:00
Info: *******************************************************************
Info: Running Quartus II TimeQuest Timing Analyzer
    Info: Version 10.1 Build 153 11/29/2010 SJ Full Version
    Info: Processing started: Mon Jan 10 21:06:23 2011
Info: Command: quartus_sta test1 -c test1
Info: qsta_default_script.tcl version: #1
Info: Parallel compilation is enabled and will use 2 of the 2 processors detected
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family
Info: Reading SDC File: 'test1.sdc'
Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
Info: The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
Warning: No clocks defined in design.
Info: No clocks to report
Info: No fmax paths to report
Info: No Setup paths to report
Info: No Hold paths to report
Info: No Recovery paths to report
Info: No Removal paths to report
Info: No Minimum Pulse Width paths to report
Info: The selected device family is not supported by the report_metastability command.
Info: Design is not fully constrained for setup requirements
Info: Design is not fully constrained for hold requirements
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 181 megabytes
    Info: Processing ended: Mon Jan 10 21:06:27 2011
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:01
Info: Quartus II Full Compilation was successful. 0 errors, 2 warnings