#include "stm32f10x.h"

ErrorStatus HSEStartUpStatus;
GPIO_InitTypeDef GPIO_InitStructure;

void RCC_Configuration(void)
{  
    // Сброс системы RCC (for debug purpose)
      RCC_DeInit();
      // Разрешение HSE
      RCC_HSEConfig(RCC_HSE_ON);
      // Ожидание готовности HSE
      HSEStartUpStatus = RCC_WaitForHSEStartUp();

      if(HSEStartUpStatus == SUCCESS)                        // Если HSE готов, то
      {
            // HCLK = SYSCLK
            RCC_HCLKConfig(RCC_SYSCLK_Div1);
            // PCLK2 = HCLK
            RCC_PCLK2Config(RCC_HCLK_Div1);
            // PCLK1 = HCLK/2
            RCC_PCLK1Config(RCC_HCLK_Div2);
            // PLLCLK = 8 МГц * 9 = 72 МГц
            RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
             // Разрешение PLL
            RCC_PLLCmd(ENABLE);
             // Ожидание готовности PLL
            while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
            {}
            // Выбор PLL как источника системного тактирования
            RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
            // Ожидание готовности PLL для использования как источника системного тактирования
            while(RCC_GetSYSCLKSource() != 0x08)
            {}
      }
}

int main(void)
{
      RCC_Configuration();                           

      RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);

      GPIO_InitStructure.GPIO_Pin =  GPIO_Pin_3;
      GPIO_InitStructure.GPIO_Speed = GPIO_Speed_10MHz;
      GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
      GPIO_Init(GPIOC, &GPIO_InitStructure);                

    while(1)
    {
            GPIO_SetBits( GPIOC, GPIO_Pin_3);
        GPIO_ResetBits( GPIOC, GPIO_Pin_3);
    }
}

             // Ожидание готовности PLL
            while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
            {}

void RCC_Configuration(void)
{  
    // Сброс системы RCC (for debug purpose)
      RCC_DeInit();
      // Разрешение HSE
      RCC_HSEConfig(RCC_HSE_ON);
      // Ожидание готовности HSE
      HSEStartUpStatus = RCC_WaitForHSEStartUp();

    // HCLK = SYSCLK
    RCC_HCLKConfig(RCC_SYSCLK_Div1);
    // PCLK2 = HCLK
    RCC_PCLK2Config(RCC_HCLK_Div1);
    // PCLK1 = HCLK/2
    RCC_PCLK1Config(RCC_HCLK_Div2);
    // PLLCLK = 8/2 МГц * 9 = 36 МГц
    RCC_PLLConfig(RCC_PLLSource_HSI_Div2, RCC_PLLMul_9);
    // Разрешение PLL
    RCC_PLLCmd(ENABLE);
    // Ожидание готовности PLL
    while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
    {}
    // Выбор PLL как источника системного тактирования
    RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
    // Ожидание готовности PLL для использования как источника системного тактирования
    while(RCC_GetSYSCLKSource() != 0x08)
    {}
}

#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
  /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices */
  /* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  
  /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices */
  /* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  
   #define STM32F10X_HD      /*!< STM32F10X_HD: STM32 High density devices */
  /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices */
  /* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */
#endif

#if !defined  USE_STDPERIPH_DRIVER
/**
* @brief Comment the line below if you will not use the peripherals drivers.
   In this case, these drivers will not be included and the application code will
   be based on direct access to peripherals registers
   */
  #define USE_STDPERIPH_DRIVER
#endif

#define FLASH_ACR_LATENCY_1 ((u8)0x02)
#define RCC_CR_HSEON ((u32)0x00010000) /* External High Speed clock enable */
#define RCC_CFGR_PLLMULL9 ((u32)0x001C0000) /* PLL input clock*9 */
#define RCC_CFGR_PLLSRC ((u32)0x00010000) /* PLL entry clock source */
#define RCC_CFGR_PPRE1_DIV2 ((u32)0x00000400) /* HCLK divided by 2 */
#define RCC_CR_HSERDY ((u32)0x00020000) /* External High Speed clock ready flag */
#define RCC_CR_PLLON ((u32)0x01000000) /* PLL enable */
#define RCC_CR_PLLRDY ((u32)0x02000000) /* PLL clock ready flag */
#define RCC_CFGR_SW_PLL ((u32)0x00000002) /* PLL selected as system clock */
#define RCC_CFGR_SWS_HSE ((u32)0x00000004) /* HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL ((u32)0x00000008) /* PLL used as system clock */

//configure clocks
FLASH->ACR |= FLASH_ACR_LATENCY_1; //flash latency = 2 wait states
RCC->CR |= RCC_CR_HSEON;
RCC->CFGR = RCC_CFGR_PLLMULL9 | RCC_CFGR_PLLSRC | RCC_CFGR_PPRE1_DIV2;
while (!(RCC->CR & RCC_CR_HSERDY));
RCC->CR |= RCC_CR_PLLON;
while (!(RCC->CR & RCC_CR_PLLRDY));
RCC->CFGR |= RCC_CFGR_SW_PLL;
while ((RCC->CFGR & (RCC_CFGR_SWS_HSE | RCC_CFGR_SWS_PLL)) != RCC_CFGR_SWS_PLL);

//Enable clocking of the peripherals - all the IO ports
RCC->APB2ENR = RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN |
RCC_APB2ENR_IOPDEN;