module scfifo_wrapper
#(parameter depth_log = 9, dw = 12, showahead = "ON")
(
input aclr,
input clock,
input [dw-1:0] data,
input rdreq,
input wrreq,
output [dw-1:0] q
);
scfifo scfifo_component
(
.aclr(aclr),
.clock(clock),
.data(data),
.rdreq(rdreq),
.wrreq(wrreq),
.q(q),
.almost_empty(),
.almost_full(),
.empty(),
.full(),
.sclr(),
.usedw()
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 2**depth_log,
scfifo_component.lpm_showahead = showahead,
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = dw,
scfifo_component.lpm_widthu = depth_log,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule

module sc_wr_ram
#(parameter num_words = 256, dw = 8)
(
input clk,
input [dw-1:0] d,
input [$clog2(num_words)-1:0] write_address,
input [$clog2(num_words)-1:0] read_address,
output reg [dw-1:0] q,
input we
);
localparam aw = $clog2(num_words);
reg [dw-1:0] mem [2**aw-1:0];
integer i;
initial begin
for (i = 0; i < 2**aw; i++)
mem[i] = '0;
end
always_ff @(posedge clk)
begin
if (we)
mem[write_address] = d;
q = mem[read_address];
end
endmodule

struct {
  logic    [7:0]     adr;
  logic    [15:0]    data;
  logic              rd;
  logic              wr;
    } bus;

wire [25:0] bus_out    = { bus.data, bus.adr, bus.rd, bus.wr };