output           select_n_to_the_sram_0;
  output           select_n_to_the_sram_1;
  output  [ 19: 0] tri_state_bridge_0_address;
  output  [  3: 0] tri_state_bridge_0_byteenablen;
  inout   [ 31: 0] tri_state_bridge_0_data;
  output           tri_state_bridge_0_readn;
  output           tri_state_bridge_0_writen;
  input            clk_0;
  input            reset_n;

Упрощенно так. У меня в верилоге некая прослойка
module w5300
(
// avalon
  inout [31:0] avs_data;
  input avs_wr_n;
  input avs_rd_n;
// conduit
inout [15:0] data;
output nwr;
output nrd;
);
assign nwr = avs_wr_n;
assign nrd = avs_rd_n;
....//// далее небольшие махинации с data (отсекание старшей части, перевод в Hiz если rd_n неактивен итп, вобщем ничего особенного)
endmodule

add_interface avalon_tristate_slave avalon_tristate end
add_interface_port avalon_tristate_slave avs_wr_n wr_n Input 1
add_interface_port avalon_tristate_slave avs_rd_n rd_n Input 1
и т д
# +-----------------------------------
# | connection point conduit_end
# |
add_interface conduit_end conduit end

set_interface_property conduit_end ENABLED true
add_interface_port conduit_end nwr export Output 1
add_interface_port conduit_end nrd export Output 1
итд

# TCL File Generated by Component Editor 10.1
# Thu Jan 27 15:05:31 OMST 2011
# DO NOT MODIFY


# +-----------------------------------
# |
# | W5300 "W5300" v1.0
# | vadimuzzz 2011.01.27.15:05:31
# |
# |
# +-----------------------------------

# +-----------------------------------
# | request TCL package from ACDS 10.1
# |
package require -exact sopc 10.1
# |
# +-----------------------------------

# +-----------------------------------
# | module W5300
# |
set_module_property NAME W5300
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP "Peripherals/Microcontroller Peripherals"
set_module_property AUTHOR vadimuzzz
set_module_property DISPLAY_NAME W5300
set_module_property INSTANTIATE_IN_SYSTEM_MODULE false
set_module_property EDITABLE true
set_module_property ANALYZE_HDL AUTO
# |
# +-----------------------------------

# +-----------------------------------
# | files
# |
# |
# +-----------------------------------

# +-----------------------------------
# | parameters
# |
# |
# +-----------------------------------

# +-----------------------------------
# | display items
# |
# |
# +-----------------------------------

# +-----------------------------------
# | connection point s0
# |
add_interface s0 avalon_tristate end
set_interface_property s0 activeCSThroughReadLatency false
set_interface_property s0 associatedClock clock
set_interface_property s0 explicitAddressSpan 0
set_interface_property s0 holdTime 0
set_interface_property s0 isMemoryDevice true
set_interface_property s0 isNonVolatileStorage false
set_interface_property s0 maximumPendingReadTransactions 0
set_interface_property s0 printableDevice false
set_interface_property s0 readLatency 2
set_interface_property s0 readWaitStates 0
set_interface_property s0 readWaitTime 0
set_interface_property s0 setupTime 0
set_interface_property s0 timingUnits Cycles
set_interface_property s0 writeWaitTime 0

set_interface_property s0 ENABLED true

add_interface_port s0 ats_s0_address address Input 9
add_interface_port s0 ats_s0_read_n read_n Input 1
add_interface_port s0 ats_s0_data data Bidir 16
add_interface_port s0 ats_s0_write_n write_n Input 1
# |
# +-----------------------------------

# +-----------------------------------
# | connection point clock
# |
add_interface clock clock end
set_interface_property clock clockRate 0

set_interface_property clock ENABLED true

add_interface_port clock clk clk Input 1
# |
# +-----------------------------------

# +-----------------------------------
# | connection point reset
# |
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT

set_interface_property reset ENABLED true

add_interface_port reset reset reset Input 1
# |
# +-----------------------------------

# +-----------------------------------
# | connection point irq0
# |
add_interface irq0 interrupt end
set_interface_property irq0 associatedAddressablePoint s0
set_interface_property irq0 associatedClock clock
set_interface_property irq0 associatedReset reset

set_interface_property irq0 ENABLED true

add_interface_port irq0 ins_irq0_irq irq Output 1
# |
# +-----------------------------------

  //Example instantiation for system 'sopc1'
  sopc1 sopc1_inst
    (
      .clk_0                         (clk_0),
      .ins_irq0_irq_from_the_W5300_0 (ins_irq0_irq_from_the_W5300_0),
      .ins_irq0_irq_from_the_W5300_1 (ins_irq0_irq_from_the_W5300_1),
      .reset_n                       (reset_n),
      .reset_to_the_W5300_0          (reset_to_the_W5300_0),
      .reset_to_the_W5300_1          (reset_to_the_W5300_1),
      .tri_state_bridge_0_address    (tri_state_bridge_0_address),
      .tri_state_bridge_0_data       (tri_state_bridge_0_data),
      .tri_state_bridge_0_readn      (tri_state_bridge_0_readn),
      .tri_state_bridge_0_writen     (tri_state_bridge_0_writen)
    );