NET "clk" TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 321.44 MHz HIGH 50%;

-- Purpose : synthesizable CRC function
-- * polynomial: (0 1 2 4 6 7 10 11 15 16 17 19 20 26 28 29 30 32)
-- * data width: 1
--
-- Info : tools@easics.be
-- http://www.easics.com
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

package PCK_CRC32_D1 is
-- polynomial: (0 1 2 4 6 7 10 11 15 16 17 19 20 26 28 29 30 32)
-- data width: 1
-- convention: the first serial bit is D[0]
function nextCRC32_D1
(Data: std_logic;
crc: std_logic_vector(31 downto 0))
return std_logic_vector;
end PCK_CRC32_D1;


package body PCK_CRC32_D1 is

-- polynomial: (0 1 2 4 6 7 10 11 15 16 17 19 20 26 28 29 30 32)
-- data width: 1
-- convention: the first serial bit is D[0]
function nextCRC32_D1
(Data: std_logic;
crc: std_logic_vector(31 downto 0))
return std_logic_vector is

variable d: std_logic_vector(0 downto 0);
variable c: std_logic_vector(31 downto 0);
variable newcrc: std_logic_vector(31 downto 0);

begin
d(0) := Data;
c := crc;

newcrc(0) := d(0) xor c(31);
newcrc(1) := d(0) xor c(0) xor c(31);
newcrc(2) := d(0) xor c(1) xor c(31);
newcrc(3) := c(2);
newcrc(4) := d(0) xor c(3) xor c(31);
newcrc(5) := c(4);
newcrc(6) := d(0) xor c(5) xor c(31);
newcrc(7) := d(0) xor c(6) xor c(31);
newcrc(8) := c(7);
newcrc(9) := c(8);
newcrc(10) := d(0) xor c(9) xor c(31);
newcrc(11) := d(0) xor c(10) xor c(31);
newcrc(12) := c(11);
newcrc(13) := c(12);
newcrc(14) := c(13);
newcrc(15) := d(0) xor c(14) xor c(31);
newcrc(16) := d(0) xor c(15) xor c(31);
newcrc(17) := d(0) xor c(16) xor c(31);
newcrc(18) := c(17);
newcrc(19) := d(0) xor c(18) xor c(31);
newcrc(20) := d(0) xor c(19) xor c(31);
newcrc(21) := c(20);
newcrc(22) := c(21);
newcrc(23) := c(22);
newcrc(24) := c(23);
newcrc(25) := c(24);
newcrc(26) := d(0) xor c(25) xor c(31);
newcrc(27) := c(26);
newcrc(28) := d(0) xor c(27) xor c(31);
newcrc(29) := d(0) xor c(28) xor c(31);
newcrc(30) := d(0) xor c(29) xor c(31);
newcrc(31) := c(30);
return newcrc;
end nextCRC32_D1;

end PCK_CRC32_D1;

-- Description : X32+X30+X29+X28+X26+X20+X19+X17+X16+X15+X11+X10+X7+X6+X4+X2+X1+1
-- 0xBA0DC66B
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity signature32 is
port(
CLK : in STD_LOGIC;
en : in STD_LOGIC;
Reset : in STD_LOGIC;
ind : in STD_LOGIC;
dat : out STD_LOGIC_VECTOR(31 downto 0)
);
end signature32;

architecture signature_body of signature32 is
signal rg_baza : STD_LOGIC_VECTOR(31 downto 0);
signal rg_bz : STD_LOGIC_VECTOR(31 downto 0);
begin
process (CLK,Reset)
begin
if Reset = '1' then
rg_baza <= "00000000000000000000000000000000";
elsif CLK'event and CLK = '1' and en = '1' then
rg_baza <= rg_bz;
end if;
end process;
rg_bz(0) <= rg_baza(31)xor ind;
rg_bz(1) <= rg_baza(0) xor (rg_baza(31) xor ind);
rg_bz(2) <= rg_baza(1) xor (rg_baza(31) xor ind);
rg_bz(3) <= rg_baza(2);
rg_bz(4) <= rg_baza(3) xor (rg_baza(31) xor ind);
rg_bz(5) <= rg_baza(4);
rg_bz(6) <= rg_baza(5) xor (rg_baza(31) xor ind);
rg_bz(7) <= rg_baza(6) xor (rg_baza(31) xor ind);
rg_bz(8) <= rg_baza(7);
rg_bz(9) <= rg_baza(8);
rg_bz(10) <= rg_baza(9) xor (rg_baza(31) xor ind);
rg_bz(11) <= rg_baza(10) xor (rg_baza(31) xor ind);
rg_bz(12) <= rg_baza(11);
rg_bz(13) <= rg_baza(12);
rg_bz(14) <= rg_baza(13);
rg_bz(15) <= rg_baza(14) xor (rg_baza(31) xor ind);
rg_bz(16) <= rg_baza(15) xor (rg_baza(31) xor ind);
rg_bz(17) <= rg_baza(16) xor (rg_baza(31) xor ind);
rg_bz(18) <= rg_baza(17);
rg_bz(19) <= rg_baza(18) xor (rg_baza(31) xor ind);
rg_bz(20) <= rg_baza(19) xor (rg_baza(31) xor ind);
rg_bz(25 downto 21) <= rg_baza(24 downto 20);
rg_bz(26) <= rg_baza(25) xor (rg_baza(31) xor ind);
rg_bz(27) <= rg_baza(26);
rg_bz(28) <= rg_baza(27) xor (rg_baza(31) xor ind);
rg_bz(29) <= rg_baza(28) xor (rg_baza(31) xor ind);
rg_bz(30) <= rg_baza(29) xor (rg_baza(31) xor ind);
rg_bz(31) <= rg_baza(30);
dat<= rg_baza;
end signature_body;