A.3. ARM7TDMI r4 example

Example A.1 shows a portion from an ARM7TDMI DSM log.eis file:

Example A.1.

24          00000050    e3c12003    BIC    r2,r1,#3

25          00000054    e2110003    ANDS   r0,r1,#3

26          00000058    e3a017c0    MOV    r1,#0xc0, 14; #0x3000000

27          0000005c    e492c004    LDR    r12,[r2],#4

28                                  Data Read          00000094    202a2a0a

30  CCFAIL  00000060    108ff180    ADDNE  pc,pc,r0,LSL #3

31          00000064    e1a00000    NOP

32          00000068    e013000c    ANDS   r0,r3,r12

33          0000006c    15c10000    STRNEB r0,[r1,#0]

34                                  Data Write Byte    03000000    0a

35          00000070    1013042c    ANDNES r0,r3,r12,LSR #8

36          00000074    15c10000    STRNEB r0,[r1,#0]

37                                  Data Write Byte    03000000    2a

38          00000078    1013082c    ANDNES r0,r3,r12,LSR #16

39          0000007c    15c10000    STRNEB r0,[r1,#0]

40                                  Data Write Byte    03000000    2a

41          00000080    10130c2c    ANDNES r0,r3,r12,LSR #24

42          00000084    1492c004    LDRNE  r12,[r2],#4

43                                  Data Read          00000098    54534554

45          00000088    15c10000    STRNEB r0,[r1,#0]

46                                  Data Write Byte    03000000    20

47          0000008c    1afffff5    BNE    {pc}-0x24; #0x68

50          00000068    e013000c    ANDS   r0,r3,r12

Cycle 26 shows a register being loaded through a constant, 0xC0, with an immediate, implied, rotate right of 14 places, and the comment field indicates that C0 rotated right by 14, that is left by 18, yields 0x03000000.

Cycle 30 shows a conditional ADD being skipped because the condition is not met. The conditional store at cycle 33 has met its condition and is therefore executed with a memory description line showing the byte value 0x0A written to address 0x03000000.

Cycle 47 shows a conditional branch at address 0x008C being taken and consequently a 3-cycle penalty occurs because the pipeline is flushed and refilled to execute the branch target instruction at address 0x0068 in cycle 50.