library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity syn is
port(
clk : in STD_LOGIC;
in_level : in STD_LOGIC;
reset : in STD_LOGIC;
imp : out STD_LOGIC
);
end syn;
architecture syn_body of syn is
signal qqq : STD_LOGIC;
signal ddd : STD_LOGIC;
begin
tg: process (clk)
begin
if clk'event and clk = '1' then
if reset='1' then
qqq <= '0';
ddd <= '0';
else
qqq <= ddd;
ddd <= in_level;
end if;
end if;
end process;
imp <= ddd xor qqq;
end syn_body;