Device Utilization Summary:

   Number of BUFGs                           9 out of 32     28%
   Number of BUFGCTRLs                       1 out of 32      3%
   Number of DCM_ADVs                        3 out of 4      75%
   Number of EMACs                           1 out of 1     100%
   Number of GT11s                           2 out of 8      25%
   Number of GT11CLKs                        1 out of 4      25%
   Number of IDELAYCTRLs                     3 out of 12     25%
      Number of LOCed IDELAYCTRLs            3 out of 3     100%

   Number of ILOGICs                        13 out of 320     4%
   Number of External IOBs                  40 out of 320    12%
      Number of LOCed IOBs                  40 out of 40    100%

   Number of External IPADs                  6 out of 344     1%
      Number of LOCed IPADs                  4 out of 6      66%

   Number of JTAGPPCs                        1 out of 1     100%
   Number of OLOGICs                        13 out of 320     4%
   Number of External OPADs                  2 out of 16     12%
      Number of LOCed OPADs                  2 out of 2     100%

   Number of PPC405_ADVs                     1 out of 1     100%
   Number of RAMB16s                        57 out of 68     83%
   Number of Slices                       3197 out of 8544   37%
      Number of SLICEMs                    132 out of 4272    3%



Overall effort level (-ol):   High
Router effort level (-rl):    High

Starting initial Timing Analysis.  REAL time: 12 secs
Finished initial Timing Analysis.  REAL time: 12 secs

Timing Score: 37738

WARNING:Par:62 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
   your design.

      Review the timing report using Timing Analyzer (In ISE select "Post-Place &
      Route Static Timing Report").  Go to the failing constraint(s) and select
      the "Timing Improvement Wizard" link for suggestions to correct each problem.

   Try the Design Goal and Strategies for Timing Performance (In ISE select Project -> Design Goals & Strategies) to
   ensure the best options are set in the tools for timing closure.

   Use the Xilinx "SmartXplorer" script to try special combinations of
   options known to produce very good results.

INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
   requested value.
Number of Timing Constraints that were not applied: 2

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing  
                                            |         |    Slack   | Achievable | Errors |    Score  
------------------------------------------------------------------------------------------------------
* TS_client_rx_clk0 = PERIOD TIMEGRP "clk_c | SETUP   |    -0.705ns|     7.905ns|      94|       33059
  lient_rx_clk0" 7.2 ns HIGH 50%            | HOLD    |     0.338ns|            |       0|           0
------------------------------------------------------------------------------------------------------
* TS_ROCKET_SYS_CLK = PERIOD TIMEGRP "ROCKE | SETUP   |    -0.585ns|     6.985ns|      24|        4679
  T_SYS_CLK" 6.4 ns HIGH 50%                | HOLD    |     0.407ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  TIMEGRP "gmii_rx_0" OFFSET = IN -6 ns VAL | SETUP   |     0.059ns|    -6.059ns|       0|           0
  ID 2 ns BEFORE COMP         "EMAC_GMII_RX | HOLD    |     0.561ns|            |       0|           0
  _CLK_0_pin"                               |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_client_tx_clk0 = PERIOD TIMEGRP "clk_c | SETUP   |     0.503ns|     6.697ns|       0|           0
  lient_tx_clk0" 7.2 ns HIGH 50%            | HOLD    |     0.411ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  TS_clock_generator_0_clock_generator_0_DC | SETUP   |     1.141ns|     8.859ns|       0|           0
  M0_CLK_OUT_0_ = PERIOD TIMEGRP         "c | HOLD    |     0.421ns|            |       0|           0
  lock_generator_0_clock_generator_0_DCM0_C |         |            |            |        |            
  LK_OUT_0_" TS_sys_clk_pin         HIGH 50 |         |            |            |        |            
  %                                         |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_phy_rx_clk0 = PERIOD TIMEGRP "clk_phy_ | SETUP   |     1.142ns|     6.058ns|       0|           0
  rx_clk0" 7.2 ns HIGH 50%                  | HOLD    |     3.214ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  TS_clock_generator_0_clock_generator_0_DC | SETUP   |     1.865ns|     3.135ns|       0|           0
  M0_CLK_OUT_5_ = PERIOD TIMEGRP         "c | HOLD    |     0.544ns|            |       0|           0
  lock_generator_0_clock_generator_0_DCM0_C |         |            |            |        |            
  LK_OUT_5_" TS_sys_clk_pin /         2 HIG |         |            |            |
       |            

  H 50%                                     |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP   |     8.852ns|     1.148ns|       0|           0
  pin" 10 ns HIGH 50%                       | HOLD    |     0.338ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  TS_dclk_50 = PERIOD TIMEGRP "dclk_50" TS_ | SETUP   |    15.046ns|     4.954ns|       0|           0
  sys_clk_pin * 2 HIGH 50%                  | HOLD    |     0.094ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  TS_mii_tx_clk0 = PERIOD TIMEGRP "clk_mii_ | SETUP   |    17.447ns|     7.553ns|       0|           0
  tx_clk0" 25 ns HIGH 50%                   | HOLD    |     1.643ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  PATH "TS_RST_ppc405_0_path" TIG           | SETUP   |         N/A|     3.922ns|     N/A|           0
------------------------------------------------------------------------------------------------------
  TS_phy_tx_clk0 = PERIOD TIMEGRP "clk_phy_ | N/A     |         N/A|         N/A|     N/A|         N/A
  tx_clk0" 7.2 ns HIGH 50%                  |         |            |            |        |            
------------------------------------------------------------------------------------------------------
  TS_clock_generator_0_clock_generator_0_DC | N/A     |         N/A|         N/A|     N/A|         N/A
  M1_CLK_OUT_7_ = PERIOD TIMEGRP         "c |         |            |            |        |            
  lock_generator_0_clock_generator_0_DCM1_C |         |            |            |        |            
  LK_OUT_7_" TS_sys_clk_pin /         1.25  |         |            |            |        |            
  HIGH 50%                                  |         |            |            |        |            
------------------------------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin                 |     10.000ns|      1.148ns|      8.859ns|            0|            0|            4|        16249|
| TS_clock_generator_0_clock_gen|     10.000ns|      8.859ns|          N/A|            0|            0|        15146|            0|
| erator_0_DCM0_CLK_OUT_0_      |             |             |             |             |             |             |             |
| TS_clock_generator_0_clock_gen|      5.000ns|      3.135ns|          N/A|            0|            0|            4|            0|
| erator_0_DCM0_CLK_OUT_5_      |             |             |             |             |             |             |             |
| TS_dclk_50                    |     20.000ns|      4.954ns|          N/A|            0|            0|         1099|            0|
| TS_clock_generator_0_clock_gen|      8.000ns|          N/A|          N/A|            0|            0|            0|            0|
| erator_0_DCM1_CLK_OUT_7_      |             |             |             |             |             |             |             |
+-------------------------------+-------------+
-------------+-------------+-------------+-------------+-------------+-------------+


2 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.


All signals are completely routed.