`define sg37E
`define x8
`define DEBUG

`include "ddr2.v"

`timescale 1 ns / 1 ps

module test ;

parameter NUM8XCHIP = 1 ;
parameter FCLK = 100000000 ;
parameter FCLK_CPU = 50000000 ;

// CPU interface
reg clk_cpu ;
reg reset ;
// address
reg [31:0] address ;
reg load_address ;
// write
reg [NUM8XCHIP*8-1:0] data_in ;
reg wren ;
wire wr_full ;
// read
wire [NUM8XCHIP*8-1:0] data_out ;
reg rden ;
wire rd_empty ;
// DDR2 interface
// reference clock
reg clk ;
// memory interface
wire [15:0] ddr2_a ;
wire [2:0] ddr2_ba ;
wire [NUM8XCHIP*8-1:0] ddr2_dq ;
wire [NUM8XCHIP-1:0] ddr2_dqs_p ;
wire [NUM8XCHIP-1:0] ddr2_dqs_n ;
wire [NUM8XCHIP-1:0] ddr2_dm ;
wire ddr2_we_n ;
wire ddr2_ras_n ;
wire ddr2_cas_n ;
wire [NUM8XCHIP-1:0] ddr2_ck_p ;
wire [NUM8XCHIP-1:0] ddr2_ck_n ;
wire ddr2_cke ;
wire ddr2_cs_n ;
wire ddr2_odt ;

genvar i ;


initial begin
clk <= 1'b0 ;
clk_cpu <= 1'b0 ;
reset <= 1'b0 ;
address <= 0 ;
load_address <= 1'b0 ;
data_in <= 0 ;
wren <= 1'b0 ;
rden <= 1'b0 ;

#250000 ;

@(posedge clk_cpu) ;
address <= #(250000000/FCLK_CPU) 0 ;
load_address <= #(250000000/FCLK_CPU) 1'b1 ;
@(posedge clk_cpu) ;
load_address <= #(250000000/FCLK_CPU) 1'b0 ;

@(posedge clk_cpu) ;
data_in <= #(250000000/FCLK_CPU) 8'hAA ;
wren <= #(250000000/FCLK_CPU) 1'b1 ;
@(posedge clk_cpu) ;
data_in <= #(250000000/FCLK_CPU) 8'hBB ;
@(posedge clk_cpu) ;
data_in <= #(250000000/FCLK_CPU) 8'hCC ;
@(posedge clk_cpu) ;
data_in <= #(250000000/FCLK_CPU) 8'hDD ;
@(posedge clk_cpu) ;
data_in <= #(250000000/FCLK_CPU) 8'h00 ;
@(posedge clk_cpu) ;
data_in <= #(250000000/FCLK_CPU) 8'h11 ;
@(posedge clk_cpu) ;
data_in <= #(250000000/FCLK_CPU) 8'h22 ;
@(posedge clk_cpu) ;
data_in <= #(250000000/FCLK_CPU) 8'h33 ;
@(posedge clk_cpu) ;
wren <= #(250000000/FCLK_CPU) 1'b0 ;

#10000 $finish ;
end

always begin
#(500000000/FCLK) clk <= ~clk ;
end

always begin
#(500000000/FCLK_CPU) clk_cpu <= ~clk_cpu ;
end


ddr2_ctrl #(
.NUM8XCHIP (NUM8XCHIP)
)

sys_ddr2_ctrl (
// CPU interface
.clk_cpu (clk_cpu),
.reset (reset),
// address
.address (address),
.load_address (load_address),
// write
.data_in (data_in),
.wren (wren),
.wr_full (wr_full),
// read
.data_out (data_out),
.rden (rden),
.rd_empty (rd_empty),
// DDR2 interface
// reference clock
.clk (clk),
// memory interface
.ddr2_a (ddr2_a),
.ddr2_ba (ddr2_ba),
.ddr2_dq (ddr2_dq),
.ddr2_dqs_p (ddr2_dqs_p),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_dm (ddr2_dm),
.ddr2_we_n (ddr2_we_n),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_cke (ddr2_cke),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_odt (ddr2_odt)
) ;

generate
for (i=0 ; i<NUM8XCHIP ; i=i+1) begin:loop_8xchip
ddr2 sys_ddr2 (
.ck (ddr2_ck_p[i]),
.ck_n (ddr2_ck_n[i]),
.cke (ddr2_cke),
.cs_n (ddr2_cs_n),
.ras_n (ddr2_ras_n),
.cas_n (ddr2_cas_n),
.we_n (ddr2_we_n),
.dm_rdqs (ddr2_dm[i]),
.ba (ddr2_ba),
.addr (ddr2_a),
.dq (ddr2_dq),
.dqs (ddr2_dqs_p[i]),
.dqs_n (ddr2_dqs_n[i]),
.rdqs_n (),
.odt (ddr2_odt)
) ;
end
endgenerate

endmodule

entity ddr2sdram is
generic(clk_pdiv:integer:=3; clk_pmul:integer:=20; debug:integer:=0);
port(
clk, rst:std_logic;
cmd_in:std_logic_vector(2 downto 0);
rdy_out:out std_logic;
addr:std_logic_vector(24 downto 0);
bank:std_logic_vector(2 downto 0);
tRP, tRTP, tRC, tRCD, tRAS, tWR, tWTR:integer;
CL:integer;
bank_out:out std_logic_vector(2 downto 0);
cmd_out:out std_logic_vector(4 downto 0);
addr_out:out std_logic_vector(13 downto 0);
odt_en:out std_logic;
dqs_read:out std_logic;
dqs_t_out: out std_logic_vector(1 downto 0)
);
end entity;

entity ddr2sdram_data is
generic(n_dqs:integer:=1; n_dqbits:integer := 4);
port(
clk, xclk, rclk, rst:in std_logic;
dq_en:std_logic_vector(1 downto 0);
data_in:in std_logic_vector(n_dqs*2*n_dqbits-1 downto 0);
data_out:out std_logic_vector(n_dqs*2*n_dqbits-1 downto 0);
dq:inout std_logic_vector(n_dqs*n_dqbits-1 downto 0);
dqs_en: std_logic_vector(1 downto 0);
dqs_read:in std_logic;
dqs:inout std_logic_vector(n_dqs-1 downto 0);
dm_in:in std_logic_vector(1 downto 0);
dm:out std_logic_vector(n_dqs-1 downto 0);
data_valid:out std_logic_vector(n_dqs-1 downto 0);
dqsxfer_o:out std_logic_vector(n_dqs-1 downto 0);
dqs_del:in std_logic
);
end entity;