# ** Error: (vsim-3389) d:/projects/fpga/arria_gx/testbench/tb.v(73): Port 'rx_digitalreset' not found in the connected module (4th connection).
#         Region: /tb/transceiver
# ** Error: (vsim-3389) d:/projects/fpga/arria_gx/testbench/tb.v(73): Port 'rx_analogreset' not found in the connected module (5th connection).
#         Region: /tb/transceiver
# ** Error: (vsim-3389) d:/projects/fpga/arria_gx/testbench/tb.v(73): Port 'tx_digitalreset' not found in the connected module (6th connection).
#         Region: /tb/transceiver
# ** Error: (vsim-3389) d:/projects/fpga/arria_gx/testbench/tb.v(73): Port 'gxb_powerdown' not found in the connected module (7th connection).
#         Region: /tb/transceiver
# ** Error: (vsim-3389) d:/projects/fpga/arria_gx/testbench/tb.v(73): Port 'pll_powerdown' not found in the connected module (8th connection).
#         Region: /tb/transceiver
# ** Error: (vsim-3389) d:/projects/fpga/arria_gx/testbench/tb.v(73): Port 'pll_locked' not found in the connected module (14th connection).
#         Region: /tb/transceiver
# ** Error: (vsim-3389) d:/projects/fpga/arria_gx/testbench/tb.v(73): Port 'rx_pll_locked' not found in the connected module (15th connection).
#         Region: /tb/transceiver
# ** Error: (vsim-3389) d:/projects/fpga/arria_gx/testbench/tb.v(73): Port 'rx_freqlocked' not found in the connected module (16th connection).
#         Region: /tb/transceiver
# ** Fatal: (vsim-3365) d:/projects/fpga/arria_gx/testbench/tb.v(73): Too many port connections. Expected 11, found 19.

vsim -L altera_mf -L lpm -L sgate -L arriaii_hssi lib/work.tb

    parameter data_rate = 792; // Mbps
    parameter data_period = (1 / (data_rate * 1e6)) * 1e9;

    task send_word;
        input [15:0] data;
        begin
                            rx_datain = data[0];
            #data_period    rx_datain = data[1];
            #data_period    rx_datain = data[2];
            #data_period    rx_datain = data[3];
            #data_period    rx_datain = data[4];
            #data_period    rx_datain = data[5];
            #data_period    rx_datain = data[6];
            #data_period    rx_datain = data[7];
            #data_period;
        end
    endtask

    // send sync pattern
     send_word(8'h 6f);
     send_word(8'h 14);

    // send data
    forever begin
        send_word(cnt);
        cnt = cnt + 1;
    end

    always @(posedge rx_clkout) if(rx_syncstatus & rx_patterndetect) rx_enapatternalign <= 0;

    fastpll fastpll
        (
            .inclk0     (pll_inclk), // pll_inclk_freq = 79.2
            .c0         (fast_clk),  // pll_inclk * 10
            .locked     ()
        );

    always @(posedge pll_inclk) begin
        cnt <= cnt + 1;
    end

    always @(posedge fast_clk) begin
        fast_bit_cnt <= fast_bit_cnt + 1;
        fast_reg <= cnt[fast_bit_cnt];
    end