always @(posedge clk or negedge Rst)
if(~Rst)
FSM_st <= IDLE;
else
FSM_st <= FSM_n;

always @(FSM_st or start or byte_cf_sent or byte_cv_sent or sstrb1 or sstrb2 or cnt_Tx_byte_clr or dout_Rx)
case(FSM_st)
IDLE:
begin
if(start)
FSM_n = TRANSMIT_CONFIGURANION_BYTE;
else
FSM_n = IDLE;
end
TRANSMIT_CONFIGURANION_BYTE:
begin
if(byte_cf_sent)
FSM_n = TRANSMIT_CONVERTION_BYTE;
else
FSM_n = TRANSMIT_CONFIGURANION_BYTE;
end
TRANSMIT_CONVERTION_BYTE:
begin
if(byte_cv_sent)
FSM_n = WAITING_MAX_WORK;
else
FSM_n = TRANSMIT_CONVERTION_BYTE;
end
WAITING_MAX_WORK:
begin
if(~sstrb1 || ~sstrb2)
FSM_n = MAX_WORK;
else
FSM_n = WAITING_MAX_WORK;
end
MAX_WORK:
begin
if(sstrb1 && sstrb2)
FSM_n = RECEIVE_DOUT;
else
FSM_n = MAX_WORK;
end
RECEIVE_DOUT:
begin
if(dout_Rx)
FSM_n = CHECK;
else
FSM_n = RECEIVE_DOUT;
end
CHECK:
begin
if(cnt_Tx_byte_clr)
FSM_n = IDLE;
else
FSM_n = TRANSMIT_CONVERTION_BYTE;
end
default:
begin
FSM_n = IDLE;
end
endcase

parameter        [6:0]        IDLE =                                             7'b0000001,
                    TRANSMIT_CONFIGURANION_BYTE = 7'b0000010,
                    TRANSMIT_CONVERTION_BYTE =       7'b0000100,
                    WAITING_MAX_WORK =                    7'b0001000,
                    MAX_WORK =                                   7'b0010000,
                    RECEIVE_DOUT =                             7'b0100000,
                    CHECK =                                          7'b1000000;