Цитата(crono @ Jul 1 2015, 21:01)
Пример бы
Не вопрос:
Код
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:27:40 06/29/2015
-- Design Name:
-- Module Name: ADD3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ADD2Full is
Port (
clk : in STD_LOGIC;
Reset : in STD_LOGIC;
PCIN: in STD_LOGIC_VECTOR (47 downto 0);
A : in STD_LOGIC_VECTOR (47 downto 0);
B : in STD_LOGIC_VECTOR (47 downto 0);
Summ : out STD_LOGIC_VECTOR (47 downto 0);
PCOUT: out STD_LOGIC_VECTOR (47 downto 0)
);
end ADD2Full;
architecture Behavioral of ADD2Full is
constant op : std_logic_vector(19 downto 0) := "10010000000000011111";
-- "10010 000 0 0000 001 11 11";
-- INMODE CARRYINSEL CIN ALUMODE opmode
-- CIN P+CIN P
begin
ADD2Full : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "NONE", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"000000000000", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000020", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "C", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 0, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 0, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 0, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 1, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 0, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 0, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 0, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 0 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PCOUT, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => Summ, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => PCIN, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
ALUMODE => op(10 downto 7), -- 4-bit input: ALU control input
CARRYINSEL => op(14 downto 12), -- 3-bit input: Carry select input
CLK => clk, -- 1-bit input: Clock input
INMODE => op(19 downto 15), -- 5-bit input: INMODE control input
OPMODE => op(6 downto 0), -- 7-bit input: Operation mode input
-- Data: 30-bit (each) input: Data Ports
A => A(47 downto 18), -- 30-bit input: A data input
B => A(17 downto 0), -- 18-bit input: B data input
C => B, -- 48-bit input: C data input
CARRYIN => op(11), -- 1-bit input: Carry input signal
D => (others => '0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '0', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '1', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '0', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '0', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEINMODE => '0', -- 1-bit input: Clock enable input for INMODEREG
CEM => '0', -- 1-bit input: Clock enable input for MREG
CEP => '0', -- 1-bit input: Clock enable input for PREG
RSTA => Reset, -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => Reset, -- 1-bit input: Reset input for BREG
RSTC => Reset, -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
end Behavioral;
Не могу запилить функцию P=A1:B1+C1+PCIN na DSP48E1 от кинтекс., Может кто чего встречал.
Jul 1 2015, 14:36
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