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[Maverick]

по ссылке отладочная плата

Key Features
SoC: ZYNQ UltraScale+ ZU9EG 900 pin packages (ZU4EV, ZU5EV, ZU7EV, ZU6EG, ZU15EG)
Memory
- 32-Bit DDR4 - 4 GByte max.
- 2 x Hyper RAM - 2 x 32 MByte max.
- SPI Boot Flash dual parallel - 512 MByte max.
- XTRMFlash (or HyperFlash) - 256 MByte max.
User I/O
- 65 x MIO, 48 x HD (all), 96 x HP (2 banks)
- Serial transceiver: GTR 4 (all) + GTH 16 (all)
- GT clocks, SYSMON I2C
- PLL clock inputs and outputs
Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
B2B connectors: 3 x 160 pin
Si5345 - 12 output PLL
All power supplies on board, single 3.3V Power required
- 14 on-board DC/DC regulators and 13 LDO's
- MSP430 power monitor and controller
- LP, FP, PL separately controlled power domains
Support for all boot modes (except NAND) and scenarios
Support for any combination of PS connected peripherals

PS эта же плата на сайте Xilinx

Just as a reminder, here’s what’s inside of a Xilinx Zynq UltraScale+ ZU9EG MPSoC:

64-bit, quad-core ARM Cortex-A53 MPCore application CPU
32-bit, dual-core ARM Cortex-R5 MPCore real-time processor
ARM Mali-400 MP2 GPU
Integrated DDR4 memory controller
Integrated high-speed ports including PCIe Gen2, USB3.0, SATA 3.0, DisplayPort, and Gigabit Ethernet
An FPGA fabric with 600K System Logic Cells, 32.1Mbits of on-chip BRAM, and 2520 DSP slices

PS PS можно в личку...