Цитата(MarYuriy @ Dec 8 2011, 12:37)

Чем отличается запись?
RCC->CFGR |= RCC_CFGR_SW_HSE; - подключит внешний тактовый вход HSE к системнным тактам SYS CLK
RCC->CFGR |= RCC_CFGR_SW;- не допускается по даташиту (см. ниже 11: not allowed)
RCC->CFGR|=RCC_CFGR_PLLSRC;- - подключит внешний тактовый вход HSE к умножителю PLL
из библиотеки STM:#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
из даташита:Bits 1:0 SW: System clock switch
Set and cleared by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving Stop and Standby mode or in case of
failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security
System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed
Bit 16 PLLSRC: PLL entry clock source
Set and cleared by software to select PLL clock source. This bit can be written only when
PLL is disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock