Вопрос по XC95288, Не до конца понимаю в чем проблема. Опции

[h0t]

Есть XC95288, (15,10ns). Пробую написать прошивку для нее. Поведенческие тесты проходят, но Post-Fit обламывается.
Есть сигнал на частоте 50MHz, он поступает на ПЛИС, но при такой частоте сигналы не устанавливаются. (переходят в состояние Х)
даже на простом делителе. Вот как это выглядит. При чем тактовые импульсы выходят так как надо.



Понимаю что этот сигнал становится тактовым но вот почему он не устанавливается пока не понимаю.

Спасибо.

Проблема видимо в задержках...

Сообщение отредактировал h0t - Feb 12 2012, 12:50

[h0t]

Смотрите есть модуль применик имеет такой код

Код

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity RS422_receiver is
    Port ( SCK : in  STD_LOGIC;
           RXD : in  STD_LOGIC;
           DATA : out  STD_LOGIC_VECTOR (6 downto 0);
           RX_READY : out  STD_LOGIC);
end RS422_receiver;

architecture Behavioral of RS422_receiver is
constant MAX_BIT_OUT : integer := 26; --максимальный размер посылки
constant DATA_COUNT : integer := 5;
constant DATA_SIZE : integer := 6;

signal RxBuf: bit_vector(DATA_SIZE downto 0); -- вектор для приема
signal prevRXD: Std_Logic;                    -- предыдущие состояние RXD (необходимо, что-бы отлавливать стартовый бит)
signal OutRxReady: Std_Logic;                           --внешний сигнал готовности приемника

signal CntRX : integer range 0 to DATA_COUNT;
signal RxBitCnt: integer range 0 to MAX_BIT_OUT;
signal RxReady: std_logic;  


begin
     process(SCK)
     variable high_count: integer range 0 to DATA_COUNT;    
     variable current_bit: bit :='0';
    
begin                            --внутренний сигнал готовности приемника
       if (rising_edge(SCK)) then  
                if (RxReady = '1' or RxReady = 'U' ) then
                        prevRXD <= RXD;
                      if (RXD='0' and prevRXD='1') then          -- Start bit,                            
                     RxBitCnt <=0;                        -- RX Bit counter
                            RxBuf<=(others=>'0');                
                            CntRX <= 1;
                            prevRXD <= '0';
                            RxReady <= '0';                    -- Start receiving    
                            --OutRxReady <= '0';
                        end if;          
                        
                     else  
                        if (RXD = '1') then high_count := high_count + 1; end if;
                            CntRX <=CntRX+1;                              
                    
                        if CntRX=DATA_COUNT-1 then    
                           if (high_count<3) then
                                current_bit := '0';
                            else
                                current_bit := '1';
                            end if;
                            high_count := 0;
                            if (RxBitCnt = 0) then
                                 RX_READY<='0';
                                 if (current_bit = '1') then        
                                        RxBuf <= (others=>'0');        
                                        RxReady <= '1';                
                                 end if;                                
                            elsif (RxBitCnt=MAX_BIT_OUT-1) then
                                 if (current_bit = '0') then
                                            RxBuf <= (others=>'0');        
                                            RxReady <= '1';    
                                            prevRXD <= RXD;
                                    else    
                                       RxReady <= '1';
                                        prevRXD <= RXD;
                                        --OutRxReady <= '1';
                                        DATA(DATA_SIZE downto 0)<= to_stdlogicvector(RxBuf(DATA_SIZE downto 0));
                                        RX_READY<='1';
                                  end if;
                            elsif (RxBitCnt=MAX_BIT_OUT-2  ) then
                                        if (current_bit = '1') then
                                            RxBuf <= (others=>'0');        
                                            RxReady <= '1';
                                            prevRXD <= RXD;                                            
                                        end if;
                            else
                                if (RxBitCnt<8) then
                                    RxBuf<= current_bit & RxBuf (DATA_SIZE downto 1) ;--- &  RxBuf(MAX_BIT_OUT downto 1);
                                end if;
                            end if;
                            
                            CntRX<= 0;                             
                            RxBitCnt <= RxBitCnt+1;
                            
                   end if;
                         end if;
        end if;
    end process;    
        

      


end Behavioral;

Этот модуль подключается к такому модулю:

Код

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Control_radiation is
    Port ( DATA : in  STD_LOGIC_VECTOR (6 downto 0);
           DATA_READY : in  STD_LOGIC;
           signal_2 : out  STD_LOGIC);
end Control_radiation;

architecture Behavioral of Control_radiation is
constant MAX_BIT_OUT : integer := 6; --максимальный размер посылки
constant CHANNEL_SIZE : integer := 64;

signal  signal2 :  STD_LOGIC;


begin
        process (DATA_READY)
        variable read_data : bit_vector (MAX_BIT_OUT downto 0);
        variable channel : integer;
        variable i: integer;
        variable ChannelOn: bit_vector(CHANNEL_SIZE-1 downto 0):=(others=>'0'); -- вектор для приема
        begin
        
            if (rising_edge(DATA_READY)) then
                read_data := to_bitvector(DATA);
                channel := conv_integer(to_stdLogicVector(read_data(5 downto 0)));                
                
                ChannelOn(channel) := read_data(6);            
                
                if ( conv_integer(to_stdLogicVector(ChannelOn(31 downto 0))) = 0 and conv_integer(to_stdLogicVector(ChannelOn(63 downto 32))) = 0 ) then
                    signal2 <= '0';
                else
                    signal2 <= '1';
                end if;
                    
            end if;
            
        end process;
        
        signal_2<='1' when signal2 = '1' else '0';

        
end Behavioral;

И при post-fit'e второй модуль не устанавливает сигналы(