Спасибо за совет.
Ситуация немного проясняется. Похоже дело в физике.
Одна плата нормально работает в данном слоте, остальные кто чаще, кто реже сбоит.
Забыл сказать это Sparat6 FG(G)484
Понял, что поставил не те кондеры по питанию GTP стоит 0.1 в ug386 минимум 0.22
Курил ераты нашел
http://www.xilinx.com/support/answers/35237.htmКак специально почти все ноги в 0 банке использую как выход (VCCO = 3.3) . Буду уменьшать токи, может поможет.
Может кто подсказать правильность задания атрибутов для GTP, может что подкрутить?
Не пойму только почему глюки проявляются в одном слоте
(ближнем к процу/мосту)
Код
--PLL Attributes
CLKINDC_B_0 => (TRUE),
CLKRCV_TRST_0 => (TRUE),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (1),
PLL_SATA_0 => (FALSE),
PLL_SOURCE_0 => "PLL0",
PLL_TXDIVSEL_OUT_0 => (1),
PLLLKDET_CFG_0 => (b"111"),
--
CLKINDC_B_1 => (TRUE),
CLKRCV_TRST_1 => (TRUE),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (1),
PLL_SATA_1 => (FALSE),
PLL_SOURCE_1 => "PLL0",
PLL_TXDIVSEL_OUT_1 => (1),
PLLLKDET_CFG_1 => (b"111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"000008000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
CLK_OUT_GTP_SEL_0 => ("TXOUTCLK0"),
TX_TDCC_CFG_0 => (b"11"),
CLK_OUT_GTP_SEL_1 => ("REFCLKPLL1"),
TX_TDCC_CFG_1 => (b"11"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"00082"), --x"80082"
TX_BUFFER_USE_0 => (TRUE),
TX_XCLK_SEL_0 => ("TXOUT"),
TXRX_INVERT_0 => (b"011"),
PMA_TX_CFG_1 => (x"00082"), --x"80082"
TX_BUFFER_USE_1 => (TRUE),
TX_XCLK_SEL_1 => ("TXOUT"),
TXRX_INVERT_1 => (b"011"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => (b"00"), --"10"
TX_IDLE_DELAY_0 => (b"011"), --"010"
CM_TRIM_1 => (b"00"), --"10"
TX_IDLE_DELAY_1 => (b"011"), --"010"
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => (b"1111"),
COM_BURST_VAL_1 => (b"1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (false),
OOBDETECT_THRESHOLD_0 => (b"111"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce048"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (true),
RCV_TERM_VTTRX_0 => (false),
RXEQ_CFG_0 => (b"01111011"),
TERMINATION_CTRL_0 => (b"10100"),
TERMINATION_OVRD_0 => (FALSE),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (FALSE),
OOBDETECT_THRESHOLD_1 => (b"111"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce048"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (true),
RCV_TERM_VTTRX_1 => (FALSE),
RXEQ_CFG_1 => (b"01111011"),
TERMINATION_CTRL_1 => (b"10100"),
TERMINATION_OVRD_1 => (FALSE),
TX_DETECT_RX_CFG_1 => (x"1832"),
--synthesis translate_off
--PRBS Detection Attributes 11.3 не знает
-- RXPRBSERR_LOOPBACK_0 => ('0'),
-- RXPRBSERR_LOOPBACK_1 => ('0'),
--synthesis translate_on
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => (b"1111111111"),
DEC_MCOMMA_DETECT_0 => (TRUE),
DEC_PCOMMA_DETECT_0 => (TRUE),
DEC_VALID_COMMA_ONLY_0 => (TRUE),
MCOMMA_10B_VALUE_0 => (b"1010000011"),
MCOMMA_DETECT_0 => (TRUE),
PCOMMA_10B_VALUE_0 => (b"0101111100"),
PCOMMA_DETECT_0 => (TRUE),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => (b"1111111111"),
DEC_MCOMMA_DETECT_1 => (TRUE),
DEC_PCOMMA_DETECT_1 => (TRUE),
DEC_VALID_COMMA_ONLY_1 => (TRUE),
MCOMMA_10B_VALUE_1 => (b"1010000011"),
MCOMMA_DETECT_1 => (TRUE),
PCOMMA_10B_VALUE_1 => (b"0101111100"),
PCOMMA_DETECT_1 => (TRUE),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (FALSE),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (FALSE),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (TRUE),
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
RX_IDLE_HI_CNT_0 => (b"1000"),
RX_IDLE_LO_CNT_0 => (b"0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (TRUE),
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
RX_IDLE_HI_CNT_1 => (b"1000"),
RX_IDLE_LO_CNT_1 => (b"0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
CLK_COR_KEEP_IDLE_0 => (FALSE),
CLK_COR_MAX_LAT_0 => (20),
CLK_COR_MIN_LAT_0 => (18),
CLK_COR_PRECEDENCE_0 => (TRUE),
CLK_COR_REPEAT_WAIT_0 => (0),
CLK_COR_SEQ_1_1_0 => (b"0100011100"),
CLK_COR_SEQ_1_2_0 => (b"0000000000"),
CLK_COR_SEQ_1_3_0 => (b"0000000000"),
CLK_COR_SEQ_1_4_0 => (b"0000000000"),
CLK_COR_SEQ_1_ENABLE_0 => (b"0001"),
CLK_COR_SEQ_2_1_0 => (b"0000000000"),
CLK_COR_SEQ_2_2_0 => (b"0000000000"),
CLK_COR_SEQ_2_3_0 => (b"0000000000"),
CLK_COR_SEQ_2_4_0 => (b"0000000000"),
CLK_COR_SEQ_2_ENABLE_0 => (b"0000"),
CLK_COR_SEQ_2_USE_0 => (FALSE),
CLK_CORRECT_USE_0 => (TRUE),
RX_DECODE_SEQ_MATCH_0 => (TRUE),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
CLK_COR_KEEP_IDLE_1 => (FALSE),
CLK_COR_MAX_LAT_1 => (20),
CLK_COR_MIN_LAT_1 => (18),
CLK_COR_PRECEDENCE_1 => (TRUE),
CLK_COR_REPEAT_WAIT_1 => (0),
CLK_COR_SEQ_1_1_1 => (b"0100011100"),
CLK_COR_SEQ_1_2_1 => (b"0000000000"),
CLK_COR_SEQ_1_3_1 => (b"0000000000"),
CLK_COR_SEQ_1_4_1 => (b"0000000000"),
CLK_COR_SEQ_1_ENABLE_1 => (b"0001"),
CLK_COR_SEQ_2_1_1 => (b"0000000000"),
CLK_COR_SEQ_2_2_1 => (b"0000000000"),
CLK_COR_SEQ_2_3_1 => (b"0000000000"),
CLK_COR_SEQ_2_4_1 => (b"0000000000"),
CLK_COR_SEQ_2_ENABLE_1 => (b"0000"),
CLK_COR_SEQ_2_USE_1 => (FALSE),
CLK_CORRECT_USE_1 => (TRUE),
RX_DECODE_SEQ_MATCH_1 => (TRUE),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
CHAN_BOND_SEQ_1_1_0 => (b"0001001010"),
CHAN_BOND_SEQ_1_2_0 => (b"0001001010"),
CHAN_BOND_SEQ_1_3_0 => (b"0001001010"),
CHAN_BOND_SEQ_1_4_0 => (b"0110111100"),
CHAN_BOND_SEQ_1_ENABLE_0 => (b"0000"),
CHAN_BOND_SEQ_2_1_0 => (b"0100111100"),
CHAN_BOND_SEQ_2_2_0 => (b"0100111100"),
CHAN_BOND_SEQ_2_3_0 => (b"0110111100"),
CHAN_BOND_SEQ_2_4_0 => (b"0100011100"),
CHAN_BOND_SEQ_2_ENABLE_0 => (b"0000"),
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (TRUE),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
CHAN_BOND_SEQ_1_1_1 => (b"0001001010"),
CHAN_BOND_SEQ_1_2_1 => (b"0001001010"),
CHAN_BOND_SEQ_1_3_1 => (b"0001001010"),
CHAN_BOND_SEQ_1_4_1 => (b"0110111100"),
CHAN_BOND_SEQ_1_ENABLE_1 => (b"0000"),
CHAN_BOND_SEQ_2_1_1 => (b"0100111100"),
CHAN_BOND_SEQ_2_2_1 => (b"0100111100"),
CHAN_BOND_SEQ_2_3_1 => (b"0110111100"),
CHAN_BOND_SEQ_2_4_1 => (b"0100011100"),
CHAN_BOND_SEQ_2_ENABLE_1 => (b"0000"),
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (TRUE),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => (b"01010"),
PCI_EXPRESS_MODE_0 => (TRUE),
RX_EN_IDLE_HOLD_CDR_0 => (TRUE),
RX_EN_IDLE_RESET_FR_0 => (TRUE),
RX_EN_IDLE_RESET_PH_0 => (TRUE),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => (b"01010"),
PCI_EXPRESS_MODE_1 => (TRUE),
RX_EN_IDLE_HOLD_CDR_1 => (TRUE),
RX_EN_IDLE_RESET_FR_1 => (TRUE),
RX_EN_IDLE_RESET_PH_1 => (TRUE),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => (b"100"),
SATA_IDLE_VAL_0 => (b"100"),
SATA_MAX_BURST_0 => (9),
SATA_MAX_INIT_0 => (27),
SATA_MAX_WAKE_0 => (9),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (15),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => (b"100"),
SATA_IDLE_VAL_1 => (b"100"),
SATA_MAX_BURST_1 => (9),
SATA_MAX_INIT_1 => (27),
SATA_MAX_WAKE_1 => (9),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (15),
SATA_MIN_WAKE_1 => (5)
Сообщение отредактировал VasiaMVR - Oct 15 2012, 18:45
PCIe сбоит в слоте для видеокарты
Oct 14 2012, 16:31
