Design reuse, without schematic Опции

[vitan]

Есть разведенная плата. Надо заимствовать ее почти целиком в новом проекте. Никаких проблем нет при наличии схемы. Но что делать, если схемы нет?
Пробовал импортировать нетлист через EDIF. Импортируется, даже создает само УГО компонентов в библиотеке, но на листы схемы их не помещает, соответственно, далее такая "схема" не пакуется и т.д. Упаковщику нужен файл .xcon (версия 16.5). При этом есть файл verilog. В хелпе сказано, что при отсутствии xcon должен автоматически запуститься процесс uprev, но этого не происходит. Вызвать его вручную я тоже не могу, нет такого файла. Как же быть?


Схема, все-таки, есть. Но она в менторовском DxD. Никак ее не удается нормально открыть в кейденсе, ни в концепте, ни в оркаде. Максимум, чего удалось добиться, это открытие схемы в криво-косом виде через EDIF, но она, ессно, не пакуется и т.д.
Кто-нибудь знает, как можно нормально отконвертировать схему и открыть ее в концепте?

[fill]

Примерно, то что показано в видео
С разницей в том что после нажатия Copy Circuit для записи выбранной топологии в обменник, нужно открыть другую плату и выполнить Paste from Layout clipboard

Solution
CMC allows user mapping of like circuits within a design.
CMC also allows copy of a circuit from one design to another with user intervention
between the designs. In this process, a temporary Expedition PCB clipboard is used to hold
the copy data
Equivalent circuitry will be matched based on:
Connectivity patterns—net names do not have to match
Part numbers—reference designators do not have to match
Terms:
Source design—design the circuit is copied from
Host design—design the circuit is copied to (may be the same as the source design)
Basic rule—Connectivity in the host design WILL NOT be changed during the copy.
Please go through the following steps to copy a circuit within or between designs.
Within Source design:
1. Issue the command Edit > Circuit Move & Copy:
2. Set the Selection Filter:
Object Filter is used to set what can be selected for the copy.
Layer filters is used to set what layers cab be select. Layers must be visible in Display
Control to be active.
3. Draw the Selection Area:
Graphic commands are used to draw a closed select area.
Chose grid from standard grid settings, refer to technote MG564125 for more
information.
Selection tools: Inside Area Extents—if unselected, any trace overlapping the
selection area shape will be selected.
Selection tools: Split Traces at Area Extents—if unselected, trace selection extends
outside selection are shape—selected trims to border edge.
Selection tools: Reset Selection—Reselect after a change in the Selection Filter.
4. (Optional)Set default manipulation origin using RMB > Set Origin, refer to techntoe
MG542625 for more information.
5. Initiate the Copy Circuit—Action Key—F7 or command Edit > Copy to Layout clipboard
The circuit is copied to the internal Expedition PCB clipboard.
Default location %USERPROFILE%\Local Settings\Temp\mgc_icc_clipboard.
User location set with a variable—MGC_LAYOUT_CLIPBOARD_PATH.
mgc_icc_clipboardis a directory holding the selected layout information.
Within Host design
6. Issue the command Edit > Paste from Layout clipboard.
7. Instantiation Wizard dialog box appears.
The default operation is for the Instantiation Wizard to automatically map all
equivalent parts in the host design. However, where connectivity in the host design
differs from the clipboard circuit, you can manually assign the equivalent elements
through the dialog box.
Ref Des Tab is used to assign parts from the source design to specific parts in the
host design.Lock: If checked, prevents the Instantiation Wizard from assigning a new
part number to a manually mapped part number.Red field: There is a component in
the clipboard circuit that has not been mapped to an equivalent part in the host
design. Component will not be placed during the instantiation. Orange field:
Component will be placed, but invalid connectivity (traces and vias) will not be
placed during instantiation.Blue field: Duplicate Reference Designator found. A
reference designator in the local design has been mapped to more than one part
found in the clipboard design.Use Same Ref Des only: This option is used for design
to design copies where the Ref Des must match in the Host design. This option can
disable the Lock option and the Resolve button. Resolve button: Tries to
automatically resolve any mapping problems.Note: Manually map a large pin count
device, prior to selecting the Resolve button, to increase the chances of resolving
mapping errors.
Nets tab can be used to map nets that cannot be mapped automatically.Floating Nets
are nets that cross the original selection area, but can not be resolved due to no
connection to the copied components.Red text indicates no available
mapping.Yellow text indicates a circuit net that contains multiple host nets.Lock: If
checked, prevents the Instantiation Wizard from assigning a new net to a manually
mapped host net.
Physical Layers tab can be used to map the Setup Parameters Dialog Box - Layer
Stackup layers in the host design that do not match the copied circuit.Allow mapping
more than one circuit layer to a one host layer Checked, enables you to map
multiple source design layers to a single host design layer.Preview is a read only list
of current mapping.
User Layers tab can be used to map user layers in the source design to user layers in
the host design. Create option: If checked, creates a new user layer in the host design
using the user layer name in the source design.
Show Report displays the InstantiationWizard.txt file report of the Wizard status.
OK button:If there are errors and warnings, you will be prompted.OK button: Returns
to the Instantiation Wizard for warnings to be resolved.Ignore button: Performs the
copy while adjusting for the warnings
8. Click left button of mouse to place the copy in the host design.

PS: Я немного ошибся ранее - эквивалентность ищется по совпадению имен компонентов и их соединениям между собой. Если совпадает, то автоматом присваивается. RefDes не имеет значения.