Начало работы с 8051 на FPGA фирмы Actel, Воопросы, возникающие при первом знакомстве с 8051. Опции

[styuf]

Предлагаю сделать тему для тех, у кого возникли вопросы при первом знакомстве с софт-микроконтролером 8051 на FPGA фирмы Actel.

И вот первые вопросы:
Как правильно подключить внутреннюю память FPGA для работы с данны микроконтролером? FPGA A3PE1500.
Хочу просто попробовать сдлеать рабочий микроконтроллер для "помигать светодиодами" на отладочнике ProASIC3 STARTER KIT. В хэндбуке сказано, что существует 4 типа памяти, из которых две должен создавать я: XDATA и CODE. Внешней памяти на плате нет, так что хочу использовать память на чипе FPGA. Интересуют настройки ядра 8051s и конфигурация памяти. Если будут какие-нибудь дополнительные вопросы по моему проекту - все расскажу и покажу)
Заранее спасибо!

Что бы быть немного конкретней: в настройка 8051 я указал память без проверки по сигналу акноледж, выбрал two ports ram без pipe-line. Сколь тактов задержки я должен указать в настройках 8051-го?

Сообщение отредактировал styuf - Apr 1 2013, 07:32

[styuf]

Извините за задержку!
Экзекуция прошла вполне успешно. В итоге даже запустил програмку, которая светила светодиодами и реагировала на кнопочки. На этом пришлось остановится, така надо было допиливать схему под ральную плату, а не играться с отладочником.
Единственное, от чего мне не по душе - отсутствие на отладочнике энергонезависимой памяти. Как следствие прошивку приходилось заливать из под SoftConsole.
Недоразабрался я с одним вопросом, непосредственно относящимся к предидущесу абзацу: почему, когда непосредственно инициализирую память в фпга перед прошивкой с помощью tools-ов либеро (то бишь в память программы я заливаю саму программу, сгенерированную компилятором), я не получаю работающей железки. Если кто-то пробовал так делать - дайте знать, буду очень благодарен.

CODE

-- test_8051.vhd
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity test_8051 is
PORT(
clock40 : in std_logic;
resetn : in std_logic;
led_out : out std_logic_vector(7 downto 0);
TCK : in std_logic;
TDI : in std_logic;
TMS : in std_logic;
TDO : out std_logic;
TRSTN : in std_logic;
test_out : out std_logic_vector(31 downto 0)
);
end test_8051;

architecture ARCH of test_8051 is
---SIGNAL---
signal clock_pll : std_logic := '0';
signal presetn, NSYSRESET : std_logic := '0';
signal int0, int1 : std_logic := '0';
---APB-SIGNAL
signal paddr : STD_LOGIC_VECTOR(23 downto 0):=(OTHERS =>'0');
signal prdata, pwdata, pwdatas : STD_LOGIC_VECTOR(31 downto 0):=(OTHERS =>'0');
signal penable, psel, pready, pslverr : STD_LOGIC;
signal paddrs, paddrs0 : STD_LOGIC_VECTOR(23 downto 0):=(OTHERS =>'0');
signal psels0, psels1, psels2, psels3, psels4, psels5, psels6, psels7, psels8, psels9, psels10, psels11, psels12, psels13, psels14, psels15 : STD_LOGIC;
signal pslverrs0, pslverrs1, pslverrs2, pslverrs3, pslverrs4, pslverrs5, pslverrs6, pslverrs7, pslverrs8, pslverrs9, pslverrs10, pslverrs11, pslverrs12, pslverrs13, pslverrs14, pslverrs15 : STD_LOGIC;
signal preadys0, preadys1, preadys2, preadys3, preadys4, preadys5, preadys6, preadys7, preadys8, preadys9, preadys10, preadys11, preadys12, preadys13, preadys14, preadys15 : STD_LOGIC;
SIGNAL pwrite, pwrites, penables: STD_LOGIC;
signal prdatas0, prdatas1, prdatas2, prdatas3, prdatas4, prdatas5, prdatas6, prdatas7, prdatas8, prdatas9, prdatas10, prdatas11, prdatas12,
prdatas13, prdatas14, prdatas15 : STD_LOGIC_VECTOR (31 downto 0):=(OTHERS =>'0');
---GPIO--signal--
SIGNAL gpio_in, gpio_out : STD_LOGIC_VECTOR(31 downto 0):=(OTHERS =>'0');
---watchdog-signal--
signal wdogres, wdogresn : STD_LOGIC;
---memory-signal---
signal dbgmempswr, mempsrd, memwr, memrd : STD_LOGIC;
signal memdatai, memdatao : std_logic_vector(7 downto 0):=(OTHERS =>'0');
signal memaddr : std_logic_vector(15 downto 0):=(OTHERS =>'0');
signal code_rd, data_rd : std_logic_vector(7 downto 0):=(OTHERS =>'0');
---
---COMPONENTS---
COMPONENT Core_8051 is
port(
CLK : in std_logic;
NSYSRESET : in std_logic;
PRESETN : out std_logic;
WDOGRES : in std_logic;
WDOGRESN : out std_logic;
INT0 : in std_logic;
INT1 : in std_logic;
MOVX : out std_logic;
---JTAG
TCK : in std_logic;
TMS : in std_logic;
TDI : in std_logic;
TDO : out std_logic;
TRSTN : in std_logic;
BREAKIN : in std_logic;
BREAKOUT : out std_logic;
TRIGOUT : out std_logic;
AUXOUT : out std_logic;
--- APB interface
PADDR : out std_logic_vector(11 downto 0);
PWDATA : out std_logic_vector(31 downto 0);
PRDATA : in std_logic_vector(31 downto 0);
PWRITE : out std_logic;
PENABLE : out std_logic;
PSEL : out std_logic;
PREADY : in std_logic;
PSLVERR : in std_logic;
---
DBGMEMPSWR : out std_logic; ---CODE memory write enable
MEMPSACKI : in std_logic; ---CODE acknowlege
MEMACKI : in std_logic; ---XDATA acknowlege
MEMPSRD : out std_logic; ---CODE memory read enable
MEMWR : out std_logic; ---XDATA memory write enable
MEMRD : out std_logic; ---XDATA memory read enable
MEMDATAI : in std_logic_vector(7 downto 0); ---CODE and XDATA memory input bus
MEMDATAO : out std_logic_vector(7 downto 0); ---CODE and XDATA memory output bus
MEMADDR : out std_logic_vector(15 downto 0);---CODE and XDATA memory address bus
MEMBANK : in std_logic_vector(3 downto 0)
);
end COMPONENT;

COMPONENT APBcore is
-- Port list
port(
-- Inputs
PADDR : in std_logic_vector(23 downto 0);
PENABLE : in std_logic;
PRDATAS0 : in std_logic_vector(31 downto 0);
PRDATAS1 : in std_logic_vector(31 downto 0);
PRDATAS10 : in std_logic_vector(31 downto 0);
PRDATAS11 : in std_logic_vector(31 downto 0);
PRDATAS12 : in std_logic_vector(31 downto 0);
PRDATAS13 : in std_logic_vector(31 downto 0);
PRDATAS14 : in std_logic_vector(31 downto 0);
PRDATAS15 : in std_logic_vector(31 downto 0);
PRDATAS2 : in std_logic_vector(31 downto 0);
PRDATAS3 : in std_logic_vector(31 downto 0);
PRDATAS4 : in std_logic_vector(31 downto 0);
PRDATAS5 : in std_logic_vector(31 downto 0);
PRDATAS6 : in std_logic_vector(31 downto 0);
PRDATAS7 : in std_logic_vector(31 downto 0);
PRDATAS8 : in std_logic_vector(31 downto 0);
PRDATAS9 : in std_logic_vector(31 downto 0);
PREADYS0 : in std_logic;
PREADYS1 : in std_logic;
PREADYS10 : in std_logic;
PREADYS11 : in std_logic;
PREADYS12 : in std_logic;
PREADYS13 : in std_logic;
PREADYS14 : in std_logic;
PREADYS15 : in std_logic;
PREADYS2 : in std_logic;
PREADYS3 : in std_logic;
PREADYS4 : in std_logic;
PREADYS5 : in std_logic;
PREADYS6 : in std_logic;
PREADYS7 : in std_logic;
PREADYS8 : in std_logic;
PREADYS9 : in std_logic;
PSEL : in std_logic;
PSLVERRS0 : in std_logic;
PSLVERRS1 : in std_logic;
PSLVERRS10 : in std_logic;
PSLVERRS11 : in std_logic;
PSLVERRS12 : in std_logic;
PSLVERRS13 : in std_logic;
PSLVERRS14 : in std_logic;
PSLVERRS15 : in std_logic;
PSLVERRS2 : in std_logic;
PSLVERRS3 : in std_logic;
PSLVERRS4 : in std_logic;
PSLVERRS5 : in std_logic;
PSLVERRS6 : in std_logic;
PSLVERRS7 : in std_logic;
PSLVERRS8 : in std_logic;
PSLVERRS9 : in std_logic;
PWDATA : in std_logic_vector(31 downto 0);
PWRITE : in std_logic;
-- Outputs
PADDRS : out std_logic_vector(23 downto 0);
PADDRS0 : out std_logic_vector(23 downto 0);
PENABLES : out std_logic;
PRDATA : out std_logic_vector(31 downto 0);
PREADY : out std_logic;
PSELS0 : out std_logic;
PSELS1 : out std_logic;
PSELS10 : out std_logic;
PSELS11 : out std_logic;
PSELS12 : out std_logic;
PSELS13 : out std_logic;
PSELS14 : out std_logic;
PSELS15 : out std_logic;
PSELS2 : out std_logic;
PSELS3 : out std_logic;
PSELS4 : out std_logic;
PSELS5 : out std_logic;
PSELS6 : out std_logic;
PSELS7 : out std_logic;
PSELS8 : out std_logic;
PSELS9 : out std_logic;
PSLVERR : out std_logic;
PWDATAS : out std_logic_vector(31 downto 0);
PWRITES : out std_logic
);
end COMPONENT;

COMPONENT WatchDog is
-- Port list
port(
-- Inputs
PADDR : in std_logic_vector(4 downto 2);
PCLK : in std_logic;
PENABLE : in std_logic;
PRESETn : in std_logic;
PSEL : in std_logic;
PWDATA : in std_logic_vector(31 downto 0);
PWRITE : in std_logic;
WDOGRESn : in std_logic;
-- Outputs
PRDATA : out std_logic_vector(31 downto 0);
WDOGRES : out std_logic
);
end COMPONENT;

COMPONENT GPIO is
-- Port list
port(
-- Inputs
GPIO_IN : in std_logic_vector(31 downto 0);
PADDR : in std_logic_vector(7 downto 0);
PCLK : in std_logic;
PENABLE : in std_logic;
PRESETN : in std_logic;
PSEL : in std_logic;
PWDATA : in std_logic_vector(31 downto 0);
PWRITE : in std_logic;
-- Outputs
GPIO_OE : out std_logic_vector(31 downto 0);
GPIO_OUT : out std_logic_vector(31 downto 0);
INT : out std_logic_vector(31 downto 0);
PRDATA : out std_logic_vector(31 downto 0);
PREADY : out std_logic;
PSLVERR : out std_logic
);
end COMPONENT;

COMPONENT Timer is
-- Port list
port(
-- Inputs
PADDR : in std_logic_vector(4 downto 2);
PCLK : in std_logic;
PENABLE : in std_logic;
PRESETn : in std_logic;
PSEL : in std_logic;
PWDATA : in std_logic_vector(31 downto 0);
PWRITE : in std_logic;
-- Outputs
PRDATA : out std_logic_vector(31 downto 0);
TIMINT : out std_logic
);
end COMPONENT;

COMPONENT RAM_4096_8 is
port( WD : in std_logic_vector(7 downto 0);
RD : out std_logic_vector(7 downto 0);
WEN : in std_logic;
REN : in std_logic;
WADDR : in std_logic_vector(11 downto 0);
RADDR : in std_logic_vector(11 downto 0);
WCLK : in std_logic;
RCLK : in std_logic;
RESET : in std_logic
);
end COMPONENT;

COMPONENT DATA_RAM_4096_8 is
port( WD : in std_logic_vector(7 downto 0);
RD : out std_logic_vector(7 downto 0);
WEN : in std_logic;
REN : in std_logic;
WADDR : in std_logic_vector(11 downto 0);
RADDR : in std_logic_vector(11 downto 0);
WCLK : in std_logic;
RCLK : in std_logic;
RESET : in std_logic
);
end COMPONENT;

COMPONENT pll_20MHz is
port( POWERDOWN : in std_logic;
CLKA : in std_logic;
LOCK : out std_logic;
GLA : out std_logic
);
end COMPONENT;

COMPONENT mem_mux is
port( Data0_port : in std_logic_vector(7 downto 0);
Data1_port : in std_logic_vector(7 downto 0);
Sel0 : in std_logic;
Result : out std_logic_vector(7 downto 0)
);
end COMPONENT;
---
begin
---DECLARATION-COMPONENT----------------------------------------------------------------------------------------------------
Core_8051_0 : Core_8051
port map(
CLK => clock_pll,
NSYSRESET => NSYSRESET,
PRESETN => presetn,
WDOGRES => '0',
WDOGRESN => OPEN,
INT0 => '0',
INT1 => '0',
MOVX => OPEN,
---JTAG
TCK => TCK,
TMS => TMS,
TDI => TDI,
TDO => TDO,
TRSTN => TRSTN,
BREAKIN => '0',
BREAKOUT => OPEN,
TRIGOUT => OPEN,
AUXOUT => OPEN,
--- APB MASTER interface
PADDR => paddr(11 downto 0),
PWDATA => pwdata,
PRDATA => prdata,
PWRITE => pwrite,
PENABLE => penable,
PSEL => psel,
PREADY => pready,
PSLVERR => pslverr,
---
DBGMEMPSWR => dbgmempswr, ---CODE memory write enable
MEMPSACKI => '1', ---CODE acknowlege
MEMACKI => '1', ---XDATA acknowlege
MEMPSRD => mempsrd, ---CODE memory read enable
MEMWR => memwr, ---XDATA memory write enable
MEMRD => memrd, ---XDATA memory read enable
MEMDATAI => memdatai, ---CODE and XDATA memory input bus
MEMDATAO => memdatao, ---CODE and XDATA memory output bus
MEMADDR => memaddr,---CODE and XDATA memory address bus
MEMBANK => (OTHERS => '0')
);
test_out(9 downto 0) <= MEMADDR(9 downto 0);
NSYSRESET <= NOT resetn;

APBcore_0 : APBcore
port map(
--Master
--in
PADDR => paddr,
PENABLE => penable,
PWDATA => pwdata,
PWRITE => pwrite,
PSEL => psel,
--out
PRDATA => prdata,
PSLVERR => pslverr,
PREADY => pready,
--Slave
-- Inputs
PRDATAS0 => prdatas0,
PRDATAS1 => prdatas1,
PRDATAS10 => prdatas10,
PRDATAS11 => prdatas11,
PRDATAS12 => prdatas12,
PRDATAS13 => prdatas13,
PRDATAS14 => prdatas14,
PRDATAS15 => prdatas15,
PRDATAS2 => prdatas2,
PRDATAS3 => prdatas3,
PRDATAS4 => prdatas4,
PRDATAS5 => prdatas5,
PRDATAS6 => prdatas6,
PRDATAS7 => prdatas7,
PRDATAS8 => prdatas8,
PRDATAS9 => prdatas9,
PREADYS0 => preadys0,
PREADYS1 => preadys1,
PREADYS10 => preadys10,
PREADYS11 => preadys11,
PREADYS12 => preadys12,
PREADYS13 => preadys13,
PREADYS14 => preadys14,
PREADYS15 => preadys15,
PREADYS2 => preadys2,
PREADYS3 => preadys3,
PREADYS4 => preadys4,
PREADYS5 => preadys5,
PREADYS6 => preadys6,
PREADYS7 => preadys7,
PREADYS8 => preadys8,
PREADYS9 => preadys9,
PSLVERRS0 => pslverrs0,
PSLVERRS1 => pslverrs1,
PSLVERRS10 => pslverrs10,
PSLVERRS11 => pslverrs11,
PSLVERRS12 => pslverrs12,
PSLVERRS13 => pslverrs13,
PSLVERRS14 => pslverrs14,
PSLVERRS15 => pslverrs15,
PSLVERRS2 => pslverrs2,
PSLVERRS3 => pslverrs3,
PSLVERRS4 => pslverrs4,
PSLVERRS5 => pslverrs5,
PSLVERRS6 => pslverrs6,
PSLVERRS7 => pslverrs7,
PSLVERRS8 => pslverrs8,
PSLVERRS9 => pslverrs9,

-- Outputs
PADDRS => paddrs,
PADDRS0 => paddrs0,
PENABLES => penables,
PSELS0 => psels0,
PSELS1 => psels1,
PSELS10 => psels10,
PSELS11 => psels11,
PSELS12 => psels12,
PSELS13 => psels13,
PSELS14 => psels14,
PSELS15 => psels15,
PSELS2 => psels2,
PSELS3 => psels3,
PSELS4 => psels4,
PSELS5 => psels5,
PSELS6 => psels6,
PSELS7 => psels7,
PSELS8 => psels8,
PSELS9 => psels9,
PWDATAS => pwdatas,
PWRITES => pwrites
);

--WatchDog_0 : WatchDog
-- port map(
-- -- Inputs
-- PCLK => clock_pll,
-- WDOGRESn => wdogresn,
-- PRESETn => presetn,
-- WDOGRES => wdogres,
-- --APB
-- PADDR => paddrs(4 downto 2),
-- PENABLE => penables,
-- PRDATA => prdatas14,
-- PSEL => psels14,
-- PWDATA => pwdatas,
-- PWRITE => pwrites
-- );

GPIO_0 : GPIO
port map(
-- Inputs

GPIO_IN => gpio_in,
PCLK => clock_pll,
-- Outputs
GPIO_OE => OPEN,
GPIO_OUT => gpio_out,
INT => OPEN,
PRESETN => presetn,
--APB
PADDR => paddrs(7 downto 0),
PENABLE => penables,
PSEL => psels2,
PWDATA => pwdatas,
PWRITE => pwrites,
PRDATA => prdatas2,
PREADY => preadys2,
PSLVERR => pslverrs2
);
test_out(17 downto 10) <= paddrs(7 downto 0);
test_out(18) <= psels2;

led_out(6 downto 0) <= gpio_out(6 downto 0);
--
--Timer_0 : Timer
-- port map(
-- -- Inputs
-- PCLK => clock_pll,
-- PRESETn => presetn,
-- -- Outputs
-- TIMINT => int0,
-- --APB
-- PENABLE => penables,
-- PADDR => paddrs(4 downto 2),
-- PRDATA => prdatas0,
-- PSEL => psels0,
-- PWDATA => pwdatas,
-- PWRITE => pwrites
-- );

CODE_RAM_4096_8 : RAM_4096_8
port map
( WD => memdatao,
RD => code_rd,
WEN => dbgmempswr,
REN => mempsrd,
WADDR => memaddr(11 downto 0),
RADDR => memaddr(11 downto 0),
WCLK => clock_pll,
RCLK => clock_pll,
RESET => '1'
);
test_out(19) <= mempsrd;
test_out(27 downto 20) <= code_rd;
DATA1_RAM_4096_8 : DATA_RAM_4096_8
port map
( WD => memdatao,
RD => data_rd,
WEN => memwr,
REN => memrd,
WADDR => memaddr(11 downto 0),
RADDR => memaddr(11 downto 0),
WCLK => clock_pll,
RCLK => clock_pll,
RESET => '1'
);

pll_20MHz_0 : pll_20MHz
port map
( POWERDOWN => '1',
CLKA => clock40,
LOCK => led_out(7),
GLA => clock_pll
);

mem_mux_0 : mem_mux
port map
( Data0_port => data_rd,
Data1_port => code_rd,
Sel0 => mempsrd,
Result => memdatai
);
---
end ARCH;

Это код топ-файла в моем проекте. Все подкомпоненты стандартные, сам я их не правил.
Если будут вопросы - спрашивайте! Постараюсь ответить.