Avalon-ST - это Avalon Streaming Interfaces, нужен Avalon-MM (Memory-Mapped), в помощь
Avalon Interface Specifications .
Компонент для SOPC builder или Qsys описывается в *_hw.tcl, рекомендую отказаться от мастера и почитать описание
для Qsys.
Как подсказку, даю пример от которого можно отталкиваться (извиняюсь писал без проверки), к компоненту подсоединяется NIOS, внутри 4 регистра: 0 - status (очередь пуста, заполнена, заполнена на половину), при чтении из 1-го происходит чтение из очереди, 2 - тестовый регистр из него всегда читается 0xAAAAAAAA, 3 - тестовый регистр в него можно писать и читать.
test_component будет виден в Qsys с версии 12.0
test_component_hw.tcl
CODE
package require -exact qsys 12.0
#------------------------------------------------------------------------------
# module
#------------------------------------------------------------------------------
set_module_property NAME test_component
set_module_property VERSION 1.0
set_module_property AUTHOR "Andrey S"
set_module_property EDITABLE false
set_module_property HIDE_FROM_SOPC true
#------------------------------------------------------------------------------
# file sets
#------------------------------------------------------------------------------
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL test_component_top
add_fileset_file "test_component.vhd" VHDL PATH "test_component.vhd"
#---------------------------------------------------------------------
# Clock & Reset connection points
#---------------------------------------------------------------------
add_interface "clk" clock end
add_interface "reset" reset end
# <interface> <property> <value>
set_interface_property "reset" associatedClock "clk"
set_interface_property "reset" synchronousEdges DEASSERT
# <interface> <port> <type> <dir> <width>
add_interface_port "clk" clk clk Input 1
add_interface_port "reset" reset reset Input 1
#---------------------------------------------------------------------
# AVALON
#---------------------------------------------------------------------
add_interface "csr" avalon slave
# <interface> <property> <value>
set_interface_property "csr" associatedClock "clk"
set_interface_property "csr" associatedReset "reset"
# <interface> <port> <type> <dir> <width>
add_interface_port "csr" bus_address address Input 2
add_interface_port "csr" bus_waitrequest waitrequest Output 1
add_interface_port "csr" bus_readdata readdata Output 32
add_interface_port "csr" bus_read read Input 1
add_interface_port "csr" bus_writedata writedata Input 32
add_interface_port "csr" bus_write write Input 1
test_component.vhd
CODE
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_component_top is
port (
clk : in std_logic;
reset : in std_logic;
bus_address : in std_logic_vector(1 downto 0);
bus_read : in std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
bus_waitrequest : out std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0)
);
end entity test_component_top;
architecture rtl of test_component_top is
signal rdreq : std_logic;
signal wrreq : std_logic;
signal rdresp : std_logic;
signal wrresp : std_logic;
-- REGS
constant C_REG_STATUS : natural := 0;
constant C_REG_RDDATA : natural := 1;
constant C_REG_TEST_AA : natural := 2;
constant C_REG_TEST : natural := 3;
signal reg_test : std_logic_vector(31 downto 0);
-- FIFO (need show-ahead)
signal fifo_q : std_logic_vector(13 downto 0);
signal fifo_rdusedw : std_logic_vector(10 downto 0);
signal fifo_rdfull : std_logic;
signal fifo_rdempty : std_logic;
signal fifo_rdreq : std_logic;
begin
process( clk, reset )
begin
if ( reset = '1' ) then
rdreq <= '0';
wrreq <= '0';
state <= ST_WAIT_REQUEST;
elsif rising_edge(clk) then
-- Default
rdreq <= '0';
wrreq <= '0';
-- State
case state is
when ST_WAIT_REQUEST =>
if ( bus_read = '1' ) then
rdreq <= '1';
state <= ST_WAIT_RESPONSE;
elsif ( bus_write = '1' ) then
wrreq <= '1';
state <= ST_WAIT_RESPONSE;
end if;
when ST_WAIT_RESPONSE =>
if ( rdresp = '1' or wrresp = '1' ) then
state <= ST_WAIT_REQUEST;
end if;
when others =>
state <= ST_WAIT_REQUEST;
end case;
end if;
end process;
bus_waitrequest <= ( bus_read or bus_write ) when ( state = ST_WAIT_REQUEST ) else not( rdresp or wrresp );
-- Write
wrresp <= wrreq;
process( clk, reset )
begin
if ( reset = '1' ) then
reg_test <= ( others => '0' );
elsif rising_edge(clk) then
if ( wrreq = '1' ) then
if ( unsigned(bus_address) = C_REG_STATUS ) then
-- Read only
elsif ( unsigned(bus_address) = C_REG_RDDATA ) then
-- Read only
elsif ( unsigned(bus_address) = C_REG_TEST_AA ) then
-- Read only
elsif ( unsigned(bus_address) = C_REG_TEST ) then
reg_test <= bus_writedata;
end if;
end if;
end if;
end process;
-- Read
process( clk, reset )
begin
if ( reset = '1' ) then
rdresp <= '0';
bus_readdata <= ( others => '0' );
elsif rising_edge(clk) then
rdresp <= rdreq;
bus_readdata <= ( others => '0' );
if ( unsigned(bus_address) = C_REG_STATUS ) then
bus_readdata(0) <= fifo_rdempty
bus_readdata(1) <= fifo_rdfull;
bus_readdata(2) <= fifo_rdusedw(fifo_rdusedw'length - 1);
elsif ( unsigned(bus_address) = C_REG_RDDATA ) then
bus_readdata(fifo_q'range) <= fifo_q;
elsif ( unsigned(bus_address) = C_REG_TEST_AA ) then
bus_readdata <= x"AAAA_AAAA";
elsif ( unsigned(bus_address) = C_REG_TEST) ) then
bus_readdata <= reg_test;
end if;
end if;
end process;
fifo_rdreq <= rdreq when ( unsigned(bus_address) = C_REG_RDDATA ) else '0';
end architecture rtl;
успехов...
Сообщение отредактировал Andrey S - Oct 29 2013, 18:40