Ошибки при работе схемы на ПЛИС, Прошу помощи. Временный задержки Опции

[bognev]

Приветсвую всех!

Возникла такая проблема и требуется помощь в ее решении.
Пишу проект на virtex 6. В проекте реализован 16 канальный DDC. Работоспособность проверена на железке.
Мне необходимо разместить на каждом канале алгоритм подавления несинхронной помехи. Сам алгоритм подавления я написал и проверил также его работоспособность. Но при размещении 16 подавителей, по 1 на каждый канал столкнулся с проблемой нехватки ресурсов slice. Решение проблемы нашел в последовательной обработке на более высокой частоте. Но при этом столнулся с другой проблемой. При отладке в ChipScope видно, что схема ведет себя не корректно. Например, счетчик считает 1 2 3 !2! 4 5 6. Возникают значения, которых не должно быть. Если в ChipScope раскрыть шину, то видно что некоторые сигналы в шине задерживаются на один такт и это приводит к ошибке. Собственно, это мой первый проект и раньше с временными задержками в схеме не сталкивался. Алгоритм синхронный и почему возникают такие задержки мне не понятно. Вопрос в том, в какую сторону копать в чем проблема и как бороться с временными задержками в ПЛИС? Так как вопрос достаточно общий, не знаю, какую информацию еще надо предоставить и в процессе обсуждения выложу ее.

Заранее благодарю за помощь.

Сообщение отредактировал bognev - Jan 22 2014, 10:40

[bognev]

Стал дальше реализовывать проект и столкнулся с новыми временными ошибками.

CODE

process(clk_0)
variable rdy_in : std_logic;
begin
if(rising_edge(clk_0)) then
if(reset_clk_0 = '1') then
rdy <= '0';
rdy_in := '0';

user_rd_data_0_0_i <= (others => '0');
user_rd_data_1_0_i <= (others => '0');
user_rd_data_2_0_i <= (others => '0');
user_rd_data_3_0_i <= (others => '0');
user_rd_data_4_0_i <= (others => '0');
user_rd_data_5_0_i <= (others => '0');
user_rd_data_6_0_i <= (others => '0');
user_rd_data_7_0_i <= (others => '0');
user_rd_data_8_0_i <= (others => '0');
user_rd_data_9_0_i <= (others => '0');
user_rd_data_10_0_i <= (others => '0');
user_rd_data_11_0_i <= (others => '0');
user_rd_data_12_0_i <= (others => '0');
user_rd_data_13_0_i <= (others => '0');
user_rd_data_14_0_i <= (others => '0');
user_rd_data_15_0_i <= (others => '0');

user_rd_data_0_1_i <= (others => '0');
user_rd_data_1_1_i <= (others => '0');
user_rd_data_2_1_i <= (others => '0');
user_rd_data_3_1_i <= (others => '0');
user_rd_data_4_1_i <= (others => '0');
user_rd_data_5_1_i <= (others => '0');
user_rd_data_6_1_i <= (others => '0');
user_rd_data_7_1_i <= (others => '0');
user_rd_data_8_1_i <= (others => '0');
user_rd_data_9_1_i <= (others => '0');
user_rd_data_10_1_i <= (others => '0');
user_rd_data_11_1_i <= (others => '0');
user_rd_data_12_1_i <= (others => '0');
user_rd_data_13_1_i <= (others => '0');
user_rd_data_14_1_i <= (others => '0');
user_rd_data_15_1_i <= (others => '0');

user_rd_data_0_2_i <= (others => '0');
user_rd_data_1_2_i <= (others => '0');
user_rd_data_2_2_i <= (others => '0');
user_rd_data_3_2_i <= (others => '0');
user_rd_data_4_2_i <= (others => '0');
user_rd_data_5_2_i <= (others => '0');
user_rd_data_6_2_i <= (others => '0');
user_rd_data_7_2_i <= (others => '0');
user_rd_data_8_2_i <= (others => '0');
user_rd_data_9_2_i <= (others => '0');
user_rd_data_10_2_i <= (others => '0');
user_rd_data_11_2_i <= (others => '0');
user_rd_data_12_2_i <= (others => '0');
user_rd_data_13_2_i <= (others => '0');
user_rd_data_14_2_i <= (others => '0');
user_rd_data_15_2_i <= (others => '0');
-----------------------------------------------------
user_rd_data_0_3_i <= (others => '0');
user_rd_data_1_3_i <= (others => '0');
user_rd_data_2_3_i <= (others => '0');
user_rd_data_3_3_i <= (others => '0');
user_rd_data_4_3_i <= (others => '0');
user_rd_data_5_3_i <= (others => '0');
user_rd_data_6_3_i <= (others => '0');
user_rd_data_7_3_i <= (others => '0');
user_rd_data_8_3_i <= (others => '0');
user_rd_data_9_3_i <= (others => '0');
user_rd_data_10_3_i <= (others => '0');
user_rd_data_11_3_i <= (others => '0');
user_rd_data_12_3_i <= (others => '0');
user_rd_data_13_3_i <= (others => '0');
user_rd_data_14_3_i <= (others => '0');
user_rd_data_15_3_i <= (others => '0');
------------------------------------------------------
user_rd_data_0_4_i <= (others => '0');
user_rd_data_1_4_i <= (others => '0');
user_rd_data_2_4_i <= (others => '0');
user_rd_data_3_4_i <= (others => '0');
user_rd_data_4_4_i <= (others => '0');
user_rd_data_5_4_i <= (others => '0');
user_rd_data_6_4_i <= (others => '0');
user_rd_data_7_4_i <= (others => '0');
user_rd_data_8_4_i <= (others => '0');
user_rd_data_9_4_i <= (others => '0');
user_rd_data_10_4_i <= (others => '0');
user_rd_data_11_4_i <= (others => '0');
user_rd_data_12_4_i <= (others => '0');
user_rd_data_13_4_i <= (others => '0');
user_rd_data_14_4_i <= (others => '0');
user_rd_data_15_4_i <= (others => '0');
------------------------------------------------------
user_rd_data_0_5_i <= (others => '0');
user_rd_data_1_5_i <= (others => '0');
user_rd_data_2_5_i <= (others => '0');
user_rd_data_3_5_i <= (others => '0');
user_rd_data_4_5_i <= (others => '0');
user_rd_data_5_5_i <= (others => '0');
user_rd_data_6_5_i <= (others => '0');
user_rd_data_7_5_i <= (others => '0');
user_rd_data_8_5_i <= (others => '0');
user_rd_data_9_5_i <= (others => '0');
user_rd_data_10_5_i <= (others => '0');
user_rd_data_11_5_i <= (others => '0');
user_rd_data_12_5_i <= (others => '0');
user_rd_data_13_5_i <= (others => '0');
user_rd_data_14_5_i <= (others => '0');
user_rd_data_15_5_i <= (others => '0');
------------------------------------------------------
user_rd_data_0_6_i <= (others => '0');
user_rd_data_1_6_i <= (others => '0');
user_rd_data_2_6_i <= (others => '0');
user_rd_data_3_6_i <= (others => '0');
user_rd_data_4_6_i <= (others => '0');
user_rd_data_5_6_i <= (others => '0');
user_rd_data_6_6_i <= (others => '0');
user_rd_data_7_6_i <= (others => '0');
user_rd_data_8_6_i <= (others => '0');
user_rd_data_9_6_i <= (others => '0');
user_rd_data_10_6_i <= (others => '0');
user_rd_data_11_6_i <= (others => '0');
user_rd_data_12_6_i <= (others => '0');
user_rd_data_13_6_i <= (others => '0');
user_rd_data_14_6_i <= (others => '0');
user_rd_data_15_6_i <= (others => '0');
------------------------------------------------------
user_rd_data_0_7_i <= (others => '0');
user_rd_data_1_7_i <= (others => '0');
user_rd_data_2_7_i <= (others => '0');
user_rd_data_3_7_i <= (others => '0');
user_rd_data_4_7_i <= (others => '0');
user_rd_data_5_7_i <= (others => '0');
user_rd_data_6_7_i <= (others => '0');
user_rd_data_7_7_i <= (others => '0');
user_rd_data_8_7_i <= (others => '0');
user_rd_data_9_7_i <= (others => '0');
user_rd_data_10_7_i <= (others => '0');
user_rd_data_11_7_i <= (others => '0');
user_rd_data_12_7_i <= (others => '0');
user_rd_data_13_7_i <= (others => '0');
user_rd_data_14_7_i <= (others => '0');
user_rd_data_15_7_i <= (others => '0');
------------------------------------------------------
user_rd_data_0_8_i <= (others => '0');
user_rd_data_1_8_i <= (others => '0');
user_rd_data_2_8_i <= (others => '0');
user_rd_data_3_8_i <= (others => '0');
user_rd_data_4_8_i <= (others => '0');
user_rd_data_5_8_i <= (others => '0');
user_rd_data_6_8_i <= (others => '0');
user_rd_data_7_8_i <= (others => '0');
user_rd_data_8_8_i <= (others => '0');
user_rd_data_9_8_i <= (others => '0');
user_rd_data_10_8_i <= (others => '0');
user_rd_data_11_8_i <= (others => '0');
user_rd_data_12_8_i <= (others => '0');
user_rd_data_13_8_i <= (others => '0');
user_rd_data_14_8_i <= (others => '0');
user_rd_data_15_8_i <= (others => '0');
------------------------------------------------------
rdy <= '0';
rdy_in := '0';
------------------------------------------------------
user_rd_data_0_0 <= (others => '0');
user_rd_data_1_0 <= (others => '0');
user_rd_data_2_0 <= (others => '0');
user_rd_data_3_0 <= (others => '0');
user_rd_data_4_0 <= (others => '0');
user_rd_data_5_0 <= (others => '0');
user_rd_data_6_0 <= (others => '0');
user_rd_data_7_0 <= (others => '0');
user_rd_data_8_0 <= (others => '0');
user_rd_data_9_0 <= (others => '0');
user_rd_data_10_0 <= (others => '0');
user_rd_data_11_0 <= (others => '0');
user_rd_data_12_0 <= (others => '0');
user_rd_data_13_0 <= (others => '0');
user_rd_data_14_0 <= (others => '0');
user_rd_data_15_0 <= (others => '0');
------------------------------------------------------
user_rd_data_0_1 <= (others => '0');
user_rd_data_1_1 <= (others => '0');
user_rd_data_2_1 <= (others => '0');
user_rd_data_3_1 <= (others => '0');
user_rd_data_4_1 <= (others => '0');
user_rd_data_5_1 <= (others => '0');
user_rd_data_6_1 <= (others => '0');
user_rd_data_7_1 <= (others => '0');
user_rd_data_8_1 <= (others => '0');
user_rd_data_9_1 <= (others => '0');
user_rd_data_10_1 <= (others => '0');
user_rd_data_11_1 <= (others => '0');
user_rd_data_12_1 <= (others => '0');
user_rd_data_13_1 <= (others => '0');
user_rd_data_14_1 <= (others => '0');
user_rd_data_15_1 <= (others => '0');
------------------------------------------------------
user_rd_data_0_2 <= (others => '0');
user_rd_data_1_2 <= (others => '0');
user_rd_data_2_2 <= (others => '0');
user_rd_data_3_2 <= (others => '0');
user_rd_data_4_2 <= (others => '0');
user_rd_data_5_2 <= (others => '0');
user_rd_data_6_2 <= (others => '0');
user_rd_data_7_2 <= (others => '0');
user_rd_data_8_2 <= (others => '0');
user_rd_data_9_2 <= (others => '0');
user_rd_data_10_2 <= (others => '0');
user_rd_data_11_2 <= (others => '0');
user_rd_data_12_2 <= (others => '0');
user_rd_data_13_2 <= (others => '0');
user_rd_data_14_2 <= (others => '0');
user_rd_data_15_2 <= (others => '0');
------------------------------------------------------
user_rd_data_0_3 <= (others => '0');
user_rd_data_1_3 <= (others => '0');
user_rd_data_2_3 <= (others => '0');
user_rd_data_3_3 <= (others => '0');
user_rd_data_4_3 <= (others => '0');
user_rd_data_5_3 <= (others => '0');
user_rd_data_6_3 <= (others => '0');
user_rd_data_7_3 <= (others => '0');
user_rd_data_8_3 <= (others => '0');
user_rd_data_9_3 <= (others => '0');
user_rd_data_10_3 <= (others => '0');
user_rd_data_11_3 <= (others => '0');
user_rd_data_12_3 <= (others => '0');
user_rd_data_13_3 <= (others => '0');
user_rd_data_14_3 <= (others => '0');
user_rd_data_15_3 <= (others => '0');
------------------------------------------------------
user_rd_data_0_4 <= (others => '0');
user_rd_data_1_4 <= (others => '0');
user_rd_data_2_4 <= (others => '0');
user_rd_data_3_4 <= (others => '0');
user_rd_data_4_4 <= (others => '0');
user_rd_data_5_4 <= (others => '0');
user_rd_data_6_4 <= (others => '0');
user_rd_data_7_4 <= (others => '0');
user_rd_data_8_4 <= (others => '0');
user_rd_data_9_4 <= (others => '0');
user_rd_data_10_4 <= (others => '0');
user_rd_data_11_4 <= (others => '0');
user_rd_data_12_4 <= (others => '0');
user_rd_data_13_4 <= (others => '0');
user_rd_data_14_4 <= (others => '0');
user_rd_data_15_4 <= (others => '0');

user_rd_data_0_5 <= (others => '0');
user_rd_data_1_5 <= (others => '0');
user_rd_data_2_5 <= (others => '0');
user_rd_data_3_5 <= (others => '0');
user_rd_data_4_5 <= (others => '0');
user_rd_data_5_5 <= (others => '0');
user_rd_data_6_5 <= (others => '0');
user_rd_data_7_5 <= (others => '0');
user_rd_data_8_5 <= (others => '0');
user_rd_data_9_5 <= (others => '0');
user_rd_data_10_5 <= (others => '0');
user_rd_data_11_5 <= (others => '0');
user_rd_data_12_5 <= (others => '0');
user_rd_data_13_5 <= (others => '0');
user_rd_data_14_5 <= (others => '0');
user_rd_data_15_5 <= (others => '0');
------------------------------------------------------
user_rd_data_0_6 <= (others => '0');
user_rd_data_1_6 <= (others => '0');
user_rd_data_2_6 <= (others => '0');
user_rd_data_3_6 <= (others => '0');
user_rd_data_4_6 <= (others => '0');
user_rd_data_5_6 <= (others => '0');
user_rd_data_6_6 <= (others => '0');
user_rd_data_7_6 <= (others => '0');
user_rd_data_8_6 <= (others => '0');
user_rd_data_9_6 <= (others => '0');
user_rd_data_10_6 <= (others => '0');
user_rd_data_11_6 <= (others => '0');
user_rd_data_12_6 <= (others => '0');
user_rd_data_13_6 <= (others => '0');
user_rd_data_14_6 <= (others => '0');
user_rd_data_15_6 <= (others => '0');

user_rd_data_0_7 <= (others => '0');
user_rd_data_1_7 <= (others => '0');
user_rd_data_2_7 <= (others => '0');
user_rd_data_3_7 <= (others => '0');
user_rd_data_4_7 <= (others => '0');
user_rd_data_5_7 <= (others => '0');
user_rd_data_6_7 <= (others => '0');
user_rd_data_7_7 <= (others => '0');
user_rd_data_8_7 <= (others => '0');
user_rd_data_9_7 <= (others => '0');
user_rd_data_10_7 <= (others => '0');
user_rd_data_11_7 <= (others => '0');
user_rd_data_12_7 <= (others => '0');
user_rd_data_13_7 <= (others => '0');
user_rd_data_14_7 <= (others => '0');
user_rd_data_15_7 <= (others => '0');
------------------------------------------------------
user_rd_data_0_8 <= (others => '0');
user_rd_data_1_8 <= (others => '0');
user_rd_data_2_8 <= (others => '0');
user_rd_data_3_8 <= (others => '0');
user_rd_data_4_8 <= (others => '0');
user_rd_data_5_8 <= (others => '0');
user_rd_data_6_8 <= (others => '0');
user_rd_data_7_8 <= (others => '0');
user_rd_data_8_8 <= (others => '0');
user_rd_data_9_8 <= (others => '0');
user_rd_data_10_8 <= (others => '0');
user_rd_data_11_8 <= (others => '0');
user_rd_data_12_8 <= (others => '0');
user_rd_data_13_8 <= (others => '0');
user_rd_data_14_8 <= (others => '0');
user_rd_data_15_8 <= (others => '0');
data_valid_i <= '0';
mpx_cmp <= "0000000";
elsif(rd_data_valid = '1') then
data_valid_i <= '1';
--if(first = '0') then
---------------------------------
case mpx_cmp is
when("0000000") =>
user_rd_data_0_0_i <= user_rd_data_rise;
user_rd_data_1_0_i <= user_rd_data_fall;
mpx_cmp <= "0000001";
when ("0000001") =>
user_rd_data_2_0_i <= user_rd_data_rise;
user_rd_data_3_0_i <= user_rd_data_fall;
mpx_cmp <= "0000010";
when("0000010") =>
user_rd_data_4_0_i <= user_rd_data_rise;
user_rd_data_5_0_i <= user_rd_data_fall;
mpx_cmp <= "0000011";
when("0000011") =>
user_rd_data_6_0_i <= user_rd_data_rise;
user_rd_data_7_0_i <= user_rd_data_fall;
mpx_cmp <= "0000100";
when("0000100") =>
user_rd_data_8_0_i <= user_rd_data_rise;
user_rd_data_9_0_i <= user_rd_data_fall;
mpx_cmp <= "0000101";
when("0000101") =>
user_rd_data_10_0_i <= user_rd_data_rise;
user_rd_data_11_0_i <= user_rd_data_fall;
mpx_cmp <= "0000110";
when("0000110") =>
user_rd_data_12_0_i <= user_rd_data_rise;
user_rd_data_13_0_i <= user_rd_data_fall;
mpx_cmp <= "0000111";
when("0000111") =>
user_rd_data_14_0_i <= user_rd_data_rise;
user_rd_data_15_0_i <= user_rd_data_fall;
mpx_cmp <= "0001000";
---------------------------------1
when("0001000") =>
user_rd_data_0_1_i <= user_rd_data_rise;
user_rd_data_1_1_i <= user_rd_data_fall;
mpx_cmp <= "0001001";
when("0001001") =>
user_rd_data_2_1_i <= user_rd_data_rise;
user_rd_data_3_1_i <= user_rd_data_fall;
mpx_cmp <= "0001010";
when("0001010") =>
user_rd_data_4_1_i <= user_rd_data_rise;
user_rd_data_5_1_i <= user_rd_data_fall;
mpx_cmp <= "0001011";
when("0001011") =>
user_rd_data_6_1_i <= user_rd_data_rise;
user_rd_data_7_1_i <= user_rd_data_fall;
mpx_cmp <= "0001100";
when("0001100") =>
user_rd_data_8_1_i <= user_rd_data_rise;
user_rd_data_9_1_i <= user_rd_data_fall;
mpx_cmp <= "0001101";
when("0001101") =>
user_rd_data_10_1_i <= user_rd_data_rise;
user_rd_data_11_1_i <= user_rd_data_fall;
mpx_cmp <= "0001110";
when("0001110") =>
user_rd_data_12_1_i <= user_rd_data_rise;
user_rd_data_13_1_i <= user_rd_data_fall;
mpx_cmp <= "0001111";
when("0001111") =>
user_rd_data_14_1_i <= user_rd_data_rise;
user_rd_data_15_1_i <= user_rd_data_fall;
mpx_cmp <= "0010000";
---------------------------------2
when("0010000") =>
user_rd_data_0_2_i <= user_rd_data_rise;
user_rd_data_1_2_i <= user_rd_data_fall;
mpx_cmp <= "0010001";
when("0010001") =>
user_rd_data_2_2_i <= user_rd_data_rise;
user_rd_data_3_2_i <= user_rd_data_fall;
mpx_cmp <= "0010010";
when("0010010") =>
user_rd_data_4_2_i <= user_rd_data_rise;
user_rd_data_5_2_i <= user_rd_data_fall;
mpx_cmp <= "0010011";
when("0010011") =>
user_rd_data_6_2_i <= user_rd_data_rise;
user_rd_data_7_2_i <= user_rd_data_fall;
mpx_cmp <= "0010100";
when("0010100") =>
user_rd_data_8_2_i <= user_rd_data_rise;
user_rd_data_9_2_i <= user_rd_data_fall;
mpx_cmp <= "0010101";
when("0010101") =>
user_rd_data_10_2_i <= user_rd_data_rise;
user_rd_data_11_2_i <= user_rd_data_fall;
mpx_cmp <= "0010110";
when("0010110") =>
user_rd_data_12_2_i <= user_rd_data_rise;
user_rd_data_13_2_i <= user_rd_data_fall;
mpx_cmp <= "0010111";
when("0010111") =>
user_rd_data_14_2_i <= user_rd_data_rise;
user_rd_data_15_2_i <= user_rd_data_fall;
mpx_cmp <= "0011111";
---------------------------------3
when("0011111") =>
user_rd_data_0_3_i <= user_rd_data_rise;
user_rd_data_1_3_i <= user_rd_data_fall;
mpx_cmp <= "0100000";
when("0100000") =>
user_rd_data_2_3_i <= user_rd_data_rise;
user_rd_data_3_3_i <= user_rd_data_fall;
mpx_cmp <= "0100001";
when("0100001") =>
user_rd_data_4_3_i <= user_rd_data_rise;
user_rd_data_5_3_i <= user_rd_data_fall;
mpx_cmp <= "0100010";
when("0100010") =>
user_rd_data_6_3_i <= user_rd_data_rise;
user_rd_data_7_3_i <= user_rd_data_fall;
mpx_cmp <= "0100011";
when("0100011") =>
user_rd_data_8_3_i <= user_rd_data_rise;
user_rd_data_9_3_i <= user_rd_data_fall;
mpx_cmp <= "0100100";
when("0100100") =>
user_rd_data_10_3_i <= user_rd_data_rise;
user_rd_data_11_3_i <= user_rd_data_fall;
mpx_cmp <= "0100101";
when("0100101") =>
user_rd_data_12_3_i <= user_rd_data_rise;
user_rd_data_13_3_i <= user_rd_data_fall;
mpx_cmp <= "0100110";
when("0100110") =>
user_rd_data_14_3_i <= user_rd_data_rise;
user_rd_data_15_3_i <= user_rd_data_fall;
mpx_cmp <= "0100111";
---------------------------------4
when("0100111") =>
user_rd_data_0_4_i <= user_rd_data_rise;
user_rd_data_1_4_i <= user_rd_data_fall;
mpx_cmp <= "0101000";
when("0101000") =>
user_rd_data_2_4_i <= user_rd_data_rise;
user_rd_data_3_4_i <= user_rd_data_fall;
mpx_cmp <= "0101001";
when("0101001") =>
user_rd_data_4_4_i <= user_rd_data_rise;
user_rd_data_5_4_i <= user_rd_data_fall;
mpx_cmp <= "0101010";
when("0101010") =>
user_rd_data_6_4_i <= user_rd_data_rise;
user_rd_data_7_4_i <= user_rd_data_fall;
mpx_cmp <= "0101011";
when("0101011") =>
user_rd_data_8_4_i <= user_rd_data_rise;
user_rd_data_9_4_i <= user_rd_data_fall;
mpx_cmp <= "0101100";
when("0101100") =>
user_rd_data_10_4_i <= user_rd_data_rise;
user_rd_data_11_4_i <= user_rd_data_fall;
mpx_cmp <= "0101101";
when("0101101") =>
user_rd_data_12_4_i <= user_rd_data_rise;
user_rd_data_13_4_i <= user_rd_data_fall;
mpx_cmp <= "0101110";
when("0101110") =>
user_rd_data_14_4_i <= user_rd_data_rise;
user_rd_data_15_4_i <= user_rd_data_fall;
mpx_cmp <= "0101111";
-------------------------------------------------------
when("0101111") =>
user_rd_data_0_5_i <= user_rd_data_rise;
user_rd_data_1_5_i <= user_rd_data_fall;
mpx_cmp <= "0110000";
when("0110000") =>
user_rd_data_2_5_i <= user_rd_data_rise;
user_rd_data_3_5_i <= user_rd_data_fall;
mpx_cmp <= "0110001";
when("0110001") =>
user_rd_data_4_5_i <= user_rd_data_rise;
user_rd_data_5_5_i <= user_rd_data_fall;
mpx_cmp <= "0110010";
when("0110010") =>
user_rd_data_6_5_i <= user_rd_data_rise;
user_rd_data_7_5_i <= user_rd_data_fall;
mpx_cmp <= "0110011";
when("0110011") =>
user_rd_data_8_5_i <= user_rd_data_rise;
user_rd_data_9_5_i <= user_rd_data_fall;
mpx_cmp <= "0110100";
when("0110100") =>
user_rd_data_10_5_i <= user_rd_data_rise;
user_rd_data_11_5_i <= user_rd_data_fall;
mpx_cmp <= "0110101";
when("0110101") =>
user_rd_data_12_5_i <= user_rd_data_rise;
user_rd_data_13_5_i <= user_rd_data_fall;
mpx_cmp <= "0110110";
when("0110110") =>
user_rd_data_14_5_i <= user_rd_data_rise;
user_rd_data_15_5_i <= user_rd_data_fall;
mpx_cmp <= "0110111";
--------------------------------------------------
when("0110111") =>
user_rd_data_0_6_i <= user_rd_data_rise;
user_rd_data_1_6_i <= user_rd_data_fall;
mpx_cmp <= "0111000";
when("0111000") =>
user_rd_data_2_6_i <= user_rd_data_rise;
user_rd_data_3_6_i <= user_rd_data_fall;
mpx_cmp <= "0111001";
when("0111001") =>
user_rd_data_4_6_i <= user_rd_data_rise;
user_rd_data_5_6_i <= user_rd_data_fall;
mpx_cmp <= "0111010";
when("0111010") =>
user_rd_data_6_6_i <= user_rd_data_rise;
user_rd_data_7_6_i <= user_rd_data_fall;
mpx_cmp <= "0111011";
when("0111011") =>
user_rd_data_8_6_i <= user_rd_data_rise;
user_rd_data_9_6_i <= user_rd_data_fall;
mpx_cmp <= "0111100";
when("0111100") =>
user_rd_data_10_6_i <= user_rd_data_rise;
user_rd_data_11_6_i <= user_rd_data_fall;
mpx_cmp <= "0111101";
when("0111101") =>
user_rd_data_12_6_i <= user_rd_data_rise;
user_rd_data_13_6_i <= user_rd_data_fall;
mpx_cmp <= "0111110";
when("0111110") =>
user_rd_data_14_6_i <= user_rd_data_rise;
user_rd_data_15_6_i <= user_rd_data_fall;
mpx_cmp <= "0111111";

when("0111111") =>
user_rd_data_0_7_i <= user_rd_data_rise;
user_rd_data_1_7_i <= user_rd_data_fall;
mpx_cmp <= "1000000";
when("1000000") =>
user_rd_data_2_7_i <= user_rd_data_rise;
user_rd_data_3_7_i <= user_rd_data_fall;
mpx_cmp <= "1000001";
when("1000001") =>
user_rd_data_4_7_i <= user_rd_data_rise;
user_rd_data_5_7_i <= user_rd_data_fall;
mpx_cmp <= "1000010";
when("1000010") =>
user_rd_data_6_7_i <= user_rd_data_rise;
user_rd_data_7_7_i <= user_rd_data_fall;
mpx_cmp <= "1000011";
when("1000011") =>
user_rd_data_8_7_i <= user_rd_data_rise;
user_rd_data_9_7_i <= user_rd_data_fall;
mpx_cmp <= "1000100";
when("1000100") =>
user_rd_data_10_7_i <= user_rd_data_rise;
user_rd_data_11_7_i <= user_rd_data_fall;
mpx_cmp <= "1000101";
when("1000101") =>
user_rd_data_12_7_i <= user_rd_data_rise;
user_rd_data_13_7_i <= user_rd_data_fall;
mpx_cmp <= "1000110";
when("1000110") =>
user_rd_data_14_7_i <= user_rd_data_rise;
user_rd_data_15_7_i <= user_rd_data_fall;
mpx_cmp <= "1000111";

when("1000111") =>
user_rd_data_0_8_i <= user_rd_data_rise;
user_rd_data_1_8_i <= user_rd_data_fall;
mpx_cmp <= "1001000";
when("1001000") =>
user_rd_data_2_8_i <= user_rd_data_rise;
user_rd_data_3_8_i <= user_rd_data_fall;
mpx_cmp <= "1001001";
when("1001001") =>
user_rd_data_4_8_i <= user_rd_data_rise;
user_rd_data_5_8_i <= user_rd_data_fall;
mpx_cmp <= "1001010";
when("1001010") =>
user_rd_data_6_8_i <= user_rd_data_rise;
user_rd_data_7_8_i <= user_rd_data_fall;
mpx_cmp <= "1001011";
when("1001011") =>
user_rd_data_8_8_i <= user_rd_data_rise;
user_rd_data_9_8_i <= user_rd_data_fall;
mpx_cmp <= "1001100";
when("1001100") =>
user_rd_data_10_8_i <= user_rd_data_rise;
user_rd_data_11_8_i <= user_rd_data_fall;
mpx_cmp <= "1001101";
when("1001101") =>
user_rd_data_12_8_i <= user_rd_data_rise;
user_rd_data_13_8_i <= user_rd_data_fall;
mpx_cmp <= "1010010";
when("1010010") =>
--user_rd_data_14_2_i <= user_rd_data_rise;
--user_rd_data_15_2_i <= user_rd_data_fall;
rdy_in := not rdy_in;
rdy <= rdy_in;

user_rd_data_0_0 <= user_rd_data_0_0_i;
user_rd_data_1_0 <= user_rd_data_1_0_i;
user_rd_data_2_0 <= user_rd_data_2_0_i;
user_rd_data_3_0 <= user_rd_data_3_0_i;
user_rd_data_4_0 <= user_rd_data_4_0_i;
user_rd_data_5_0 <= user_rd_data_5_0_i;
user_rd_data_6_0 <= user_rd_data_6_0_i;
user_rd_data_7_0 <= user_rd_data_7_0_i;
user_rd_data_8_0 <= user_rd_data_8_0_i;
user_rd_data_9_0 <= user_rd_data_9_0_i;
user_rd_data_10_0 <= user_rd_data_10_0_i;
user_rd_data_11_0 <= user_rd_data_11_0_i;
user_rd_data_12_0 <= user_rd_data_12_0_i;
user_rd_data_13_0 <= user_rd_data_13_0_i;
user_rd_data_14_0 <= user_rd_data_14_0_i;
user_rd_data_15_0 <= user_rd_data_15_0_i;

user_rd_data_0_1 <= user_rd_data_0_1_i;
user_rd_data_1_1 <= user_rd_data_1_1_i;
user_rd_data_2_1 <= user_rd_data_2_1_i;
user_rd_data_3_1 <= user_rd_data_3_1_i;
user_rd_data_4_1 <= user_rd_data_4_1_i;
user_rd_data_5_1 <= user_rd_data_5_1_i;
user_rd_data_6_1 <= user_rd_data_6_1_i;
user_rd_data_7_1 <= user_rd_data_7_1_i;
user_rd_data_8_1 <= user_rd_data_8_1_i;
user_rd_data_9_1 <= user_rd_data_9_1_i;
user_rd_data_10_1 <= user_rd_data_10_1_i;
user_rd_data_11_1 <= user_rd_data_11_1_i;
user_rd_data_12_1 <= user_rd_data_12_1_i;
user_rd_data_13_1 <= user_rd_data_13_1_i;
user_rd_data_14_1 <= user_rd_data_14_1_i;
user_rd_data_15_1 <= user_rd_data_15_1_i;

user_rd_data_0_2 <= user_rd_data_0_2_i;
user_rd_data_1_2 <= user_rd_data_1_2_i;
user_rd_data_2_2 <= user_rd_data_2_2_i;
user_rd_data_3_2 <= user_rd_data_3_2_i;
user_rd_data_4_2 <= user_rd_data_4_2_i;
user_rd_data_5_2 <= user_rd_data_5_2_i;
user_rd_data_6_2 <= user_rd_data_6_2_i;
user_rd_data_7_2 <= user_rd_data_7_2_i;
user_rd_data_8_2 <= user_rd_data_8_2_i;
user_rd_data_9_2 <= user_rd_data_9_2_i;
user_rd_data_10_2 <= user_rd_data_10_2_i;
user_rd_data_11_2 <= user_rd_data_11_2_i;
user_rd_data_12_2 <= user_rd_data_12_2_i;
user_rd_data_13_2 <= user_rd_data_13_2_i;
user_rd_data_14_2 <= user_rd_data_14_2_i;
user_rd_data_15_2 <= user_rd_data_15_2_i;

user_rd_data_0_3 <= user_rd_data_0_3_i;
user_rd_data_1_3 <= user_rd_data_1_3_i;
user_rd_data_2_3 <= user_rd_data_2_3_i;
user_rd_data_3_3 <= user_rd_data_3_3_i;
user_rd_data_4_3 <= user_rd_data_4_3_i;
user_rd_data_5_3 <= user_rd_data_5_3_i;
user_rd_data_6_3 <= user_rd_data_6_3_i;
user_rd_data_7_3 <= user_rd_data_7_3_i;
user_rd_data_8_3 <= user_rd_data_8_3_i;
user_rd_data_9_3 <= user_rd_data_9_3_i;
user_rd_data_10_3 <= user_rd_data_10_3_i;
user_rd_data_11_3 <= user_rd_data_11_3_i;
user_rd_data_12_3 <= user_rd_data_12_3_i;
user_rd_data_13_3 <= user_rd_data_13_3_i;
user_rd_data_14_3 <= user_rd_data_14_3_i;
user_rd_data_15_3 <= user_rd_data_15_3_i;

user_rd_data_0_4 <= user_rd_data_0_4_i;
user_rd_data_1_4 <= user_rd_data_1_4_i;
user_rd_data_2_4 <= user_rd_data_2_4_i;
user_rd_data_3_4 <= user_rd_data_3_4_i;
user_rd_data_4_4 <= user_rd_data_4_4_i;
user_rd_data_5_4 <= user_rd_data_5_4_i;
user_rd_data_6_4 <= user_rd_data_6_4_i;
user_rd_data_7_4 <= user_rd_data_7_4_i;
user_rd_data_8_4 <= user_rd_data_8_4_i;
user_rd_data_9_4 <= user_rd_data_9_4_i;
user_rd_data_10_4 <= user_rd_data_10_4_i;
user_rd_data_11_4 <= user_rd_data_11_4_i;
user_rd_data_12_4 <= user_rd_data_12_4_i;
user_rd_data_13_4 <= user_rd_data_13_4_i;
user_rd_data_14_4 <= user_rd_data_14_4_i;
user_rd_data_15_4 <= user_rd_data_15_4_i;

user_rd_data_0_5 <= user_rd_data_0_5_i;
user_rd_data_1_5 <= user_rd_data_1_5_i;
user_rd_data_2_5 <= user_rd_data_2_5_i;
user_rd_data_3_5 <= user_rd_data_3_5_i;
user_rd_data_4_5 <= user_rd_data_4_5_i;
user_rd_data_5_5 <= user_rd_data_5_5_i;
user_rd_data_6_5 <= user_rd_data_6_5_i;
user_rd_data_7_5 <= user_rd_data_7_5_i;
user_rd_data_8_5 <= user_rd_data_8_5_i;
user_rd_data_9_5 <= user_rd_data_9_5_i;
user_rd_data_10_5 <= user_rd_data_10_5_i;
user_rd_data_11_5 <= user_rd_data_11_5_i;
user_rd_data_12_5 <= user_rd_data_12_5_i;
user_rd_data_13_5 <= user_rd_data_13_5_i;
user_rd_data_14_5 <= user_rd_data_14_5_i;
user_rd_data_15_5 <= user_rd_data_15_5_i;

user_rd_data_0_6 <= user_rd_data_0_6_i;
user_rd_data_1_6 <= user_rd_data_1_6_i;
user_rd_data_2_6 <= user_rd_data_2_6_i;
user_rd_data_3_6 <= user_rd_data_3_6_i;
user_rd_data_4_6 <= user_rd_data_4_6_i;
user_rd_data_5_6 <= user_rd_data_5_6_i;
user_rd_data_6_6 <= user_rd_data_6_6_i;
user_rd_data_7_6 <= user_rd_data_7_6_i;
user_rd_data_8_6 <= user_rd_data_8_6_i;
user_rd_data_9_6 <= user_rd_data_9_6_i;
user_rd_data_10_6 <= user_rd_data_10_6_i;
user_rd_data_11_6 <= user_rd_data_11_6_i;
user_rd_data_12_6 <= user_rd_data_12_6_i;
user_rd_data_13_6 <= user_rd_data_13_6_i;
user_rd_data_14_6 <= user_rd_data_14_6_i;
user_rd_data_15_6 <= user_rd_data_15_6_i;

user_rd_data_0_7 <= user_rd_data_0_7_i;
user_rd_data_1_7 <= user_rd_data_1_7_i;
user_rd_data_2_7 <= user_rd_data_2_7_i;
user_rd_data_3_7 <= user_rd_data_3_7_i;
user_rd_data_4_7 <= user_rd_data_4_7_i;
user_rd_data_5_7 <= user_rd_data_5_7_i;
user_rd_data_6_7 <= user_rd_data_6_7_i;
user_rd_data_7_7 <= user_rd_data_7_7_i;
user_rd_data_8_7 <= user_rd_data_8_7_i;
user_rd_data_9_7 <= user_rd_data_9_7_i;
user_rd_data_10_7 <= user_rd_data_10_7_i;
user_rd_data_11_7 <= user_rd_data_11_7_i;
user_rd_data_12_7 <= user_rd_data_12_7_i;
user_rd_data_13_7 <= user_rd_data_13_7_i;
user_rd_data_14_7 <= user_rd_data_14_7_i;
user_rd_data_15_7 <= user_rd_data_15_7_i;

user_rd_data_0_8_l <= user_rd_data_0_8_i;
user_rd_data_1_8_l <= user_rd_data_1_8_i;
user_rd_data_2_8_l <= user_rd_data_2_8_i;
user_rd_data_3_8_l <= user_rd_data_3_8_i;
user_rd_data_4_8_l <= user_rd_data_4_8_i;
user_rd_data_5_8_l <= user_rd_data_5_8_i;
user_rd_data_6_8_l <= user_rd_data_6_8_i;
user_rd_data_7_8_l <= user_rd_data_7_8_i;
user_rd_data_8_8_l <= user_rd_data_8_8_i;
user_rd_data_9_8_l <= user_rd_data_9_8_i;
user_rd_data_10_8_l <= user_rd_data_10_8_i;
user_rd_data_11_8_l <= user_rd_data_11_8_i;
user_rd_data_12_8_l <= user_rd_data_12_8_i;
user_rd_data_13_8_l <= user_rd_data_13_8_i;
user_rd_data_14_8_l <= user_rd_data_rise;
user_rd_data_15_8_l <= user_rd_data_fall;


user_rd_data_0_8 <= user_rd_data_0_8_l;
user_rd_data_1_8 <= user_rd_data_1_8_l;
user_rd_data_2_8 <= user_rd_data_2_8_l;
user_rd_data_3_8 <= user_rd_data_3_8_l;
user_rd_data_4_8 <= user_rd_data_4_8_l;
user_rd_data_5_8 <= user_rd_data_5_8_l;
user_rd_data_6_8 <= user_rd_data_6_8_l;
user_rd_data_7_8 <= user_rd_data_7_8_l;
user_rd_data_8_8 <= user_rd_data_8_8_l;
user_rd_data_9_8 <= user_rd_data_9_8_l;
user_rd_data_10_8 <= user_rd_data_10_8_l;
user_rd_data_11_8 <= user_rd_data_11_8_l;
user_rd_data_12_8 <= user_rd_data_12_8_l;
user_rd_data_13_8 <= user_rd_data_13_8_l;
user_rd_data_14_8 <= user_rd_data_14_8_l;
user_rd_data_15_8 <= user_rd_data_15_8_l;
mpx_cmp <= "0000000";
when others => NULL;
end case;
end if;
end if;
end process;
;

Вот в этой части кода я данные по сигналу rd_data_valid с памяти последовательно записываю в регистры и параллельно выдаю по окончании.
Не могли бы вы подсказать насколько данный код не оптимален? И в чем? И как правильно организовать преобразование последоветельного потока данных в параллельный?

CODE

Timing constraint: PERIOD analysis for net "clk200x" derived from NET "clk100" PERIOD = 10 ns HIGH 50%; divided by 2.00 to 5 nS
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
191470397 paths analyzed, 17155 endpoints analyzed, 1066 failing endpoints
1066 timing errors detected. (1061 setup errors, 5 hold errors, 0 component switching limit errors)
Minimum period is 5.956ns.
--------------------------------------------------------------------------------

Paths for end point ddc/ddc/IMPCI/U2/U2/blk00000337 (SLICE_X64Y150.CIN), 1810530 paths
--------------------------------------------------------------------------------
Slack (setup path): -0.956ns (requirement - (data path - clock path skew + uncertainty))
Source: ddc/ddc/SW_IN_I/Label1/U15/outp_20 (FF)
Destination: ddc/ddc/IMPCI/U2/U2/blk00000337 (FF)
Requirement: 5.000ns
Data Path Delay: 5.833ns (Levels of Logic = 9)
Clock Path Skew: -0.051ns (0.893 - 0.944)
Source Clock: clk200 rising at 0.000ns
Destination Clock: clk200 rising at 5.000ns
Clock Uncertainty: 0.072ns

Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.124ns
Phase Error (PE): 0.000ns

Maximum Data Path at Slow Process Corner: ddc/ddc/SW_IN_I/Label1/U15/outp_20 to ddc/ddc/IMPCI/U2/U2/blk00000337
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X67Y143.DQ Tcko 0.337 ddc/ddc/SW_IN_I/Label1/U15/outp<20>
ddc/ddc/SW_IN_I/Label1/U15/outp_20
SLICE_X60Y143.B2 net (fanout=34) 0.952 ddc/ddc/SW_IN_I/Label1/U15/outp<20>
SLICE_X60Y143.COUT Topcyb 0.406 ddc/ddc/IMPCI/U2/U2/sig0000030e
ddc/ddc/IMPCI/U2/U2/blk000003a5
ddc/ddc/IMPCI/U2/U2/blk000000fa
SLICE_X60Y144.CIN net (fanout=1) 0.000 ddc/ddc/IMPCI/U2/U2/sig0000030e
SLICE_X60Y144.DMUX Tcind 0.316 ddc/ddc/IMPCI/U2/U2/sig000002ee
ddc/ddc/IMPCI/U2/U2/blk000000da
SLICE_X59Y145.B3 net (fanout=2) 0.470 ddc/ddc/IMPCI/U2/U2/sig00000247
SLICE_X59Y145.COUT Topcyb 0.404 ddc/ddc/u_ddrii_tb_top_0/Label1/user_rd_data_11_1_i<20>
ddc/ddc/IMPCI/U2/U2/blk000002f2
ddc/ddc/IMPCI/U2/U2/blk000002eb
SLICE_X59Y146.CIN net (fanout=1) 0.000 ddc/ddc/IMPCI/U2/U2/sig000000db
SLICE_X59Y146.CMUX Tcinc 0.243 ddc/ddc/u_ddrii_tb_top_0/Label1/user_rd_data_2_1_i<25>
ddc/ddc/IMPCI/U2/U2/blk000002df
SLICE_X65Y147.A4 net (fanout=1) 0.914 ddc/ddc/IMPCI/U2/U2/sig0000018d
SLICE_X65Y147.COUT Topcya 0.409 ddc/ddc/u_ddrii_tb_top_0/Label1/user_rd_data_10_1<8>
ddc/ddc/IMPCI/U2/U2/blk0000023e
ddc/ddc/IMPCI/U2/U2/blk00000234
SLICE_X65Y148.CIN net (fanout=1) 0.000 ddc/ddc/IMPCI/U2/U2/sig00000062
SLICE_X65Y148.DMUX Tcind 0.315 ddc/ddc/u_ddrii_tb_top_0/Label1/user_rd_data_0_1_i<2>
ddc/ddc/IMPCI/U2/U2/blk00000228
SLICE_X64Y148.D4 net (fanout=2) 0.530 ddc/ddc/IMPCI/U2/U2/sig0000015f
SLICE_X64Y148.COUT Topcyd 0.319 ddc/ddc/IMPCI/U2/BUS47<23>
ddc/ddc/IMPCI/U2/U2/blk000001bc
ddc/ddc/IMPCI/U2/U2/blk000001bb
SLICE_X64Y149.CIN net (fanout=1) 0.000 ddc/ddc/IMPCI/U2/U2/sig00000012
SLICE_X64Y149.COUT Tbyp 0.078 ddc/ddc/IMPCI/U2/BUS47<27>
ddc/ddc/IMPCI/U2/U2/blk000001af
SLICE_X64Y150.CIN net (fanout=1) 0.000 ddc/ddc/IMPCI/U2/U2/sig0000000a
SLICE_X64Y150.CLK Tcinck 0.140 ddc/ddc/IMPCI/U2/BUS47<31>
ddc/ddc/IMPCI/U2/U2/blk000001a3
ddc/ddc/IMPCI/U2/U2/blk00000337
------------------------------------------------- ---------------------------
Total 5.833ns (2.967ns logic, 2.866ns route)
(50.9% logic, 49.1% route)

CODE

Paths for end point ddc/ddc/IMPCI/U9/blk00000003 (DSP48_X4Y39.PCIN0), 17 paths
--------------------------------------------------------------------------------
Slack (setup path): -0.938ns (requirement - (data path - clock path skew + uncertainty))
Source: ddc/ddc/IMPCI/U8/median_5 (FF)
Destination: ddc/ddc/IMPCI/U9/blk00000003 (DSP)
Requirement: 5.000ns
Data Path Delay: 5.874ns (Levels of Logic = 1)(Component delays alone exceeds constraint)
Clock Path Skew: 0.008ns (0.904 - 0.896)
Source Clock: clk200 rising at 0.000ns
Destination Clock: clk200 rising at 5.000ns
Clock Uncertainty: 0.072ns

Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.124ns
Phase Error (PE): 0.000ns

Maximum Data Path at Slow Process Corner: ddc/ddc/IMPCI/U8/median_5 to ddc/ddc/IMPCI/U9/blk00000003
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X81Y96.BMUX Tshcko 0.420 ddc/ddc/IMPCI/U8/median<11>
ddc/ddc/IMPCI/U8/median_5
DSP48_X4Y38.B5 net (fanout=1) 0.423 ddc/ddc/IMPCI/U8/median<5>
DSP48_X4Y38.PCOUT0 Tdspdo_B_PCOUT_MULT 3.691 ddc/ddc/IMPCI/U9/blk00000004
ddc/ddc/IMPCI/U9/blk00000004
DSP48_X4Y39.PCIN0 net (fanout=1) 0.002 ddc/ddc/IMPCI/U9/sig00000003
DSP48_X4Y39.CLK Tdspdck_PCIN_PREG 1.338 ddc/ddc/IMPCI/U9/blk00000003
ddc/ddc/IMPCI/U9/blk00000003
------------------------------------------------- ---------------------------
Total 5.874ns (5.449ns logic, 0.425ns route)
(92.8% logic, 7.2% route)

У меня в схеме есть две разных корки умножителя на DSP48 с оптимальным pipeline. У меня получается такая закономерность, что при синтезе пути к этим умножителям страдают от временных ошибок. Из за чего такое может быть?

Сообщение отредактировал bognev - Jan 31 2014, 04:52

[Джеймс]

Стал дальше реализовывать проект и столкнулся с новыми временными ошибками.

Не могли бы вы подсказать насколько данный код не оптимален? И в чем? И как правильно организовать преобразование последоветельного потока данных в параллельный?

Замените мультиплексор на регистр сдвига. Так вы по крайней мере избавитесь от огромного разветвления user_rd_data_rise, user_rd_data_fall.
Имею в виду вот это:

Код

        when("1001010") =>
                    user_rd_data_6_8_i <= user_rd_data_rise;
                    user_rd_data_7_8_i <= user_rd_data_fall;
                    mpx_cmp <= "1001011";                   
                when("1001011") =>
                    user_rd_data_8_8_i <= user_rd_data_rise;
                    user_rd_data_9_8_i <= user_rd_data_fall;

P.S. Старайтесь везде указывать разрядность.. Полезная привычка.

[bognev]

Замените мультиплексор на регистр сдвига. Так вы по крайней мере избавитесь от огромного разветвления user_rd_data_rise, user_rd_data_fall.
Имею в виду вот это:

Код

        when("1001010") =>
                    user_rd_data_6_8_i <= user_rd_data_rise;
                    user_rd_data_7_8_i <= user_rd_data_fall;
                    mpx_cmp <= "1001011";                   
                when("1001011") =>
                    user_rd_data_8_8_i <= user_rd_data_rise;
                    user_rd_data_9_8_i <= user_rd_data_fall;

P.S. Старайтесь везде указывать разрядность.. Полезная привычка.

Разрядность шин 36 бит.

Я заменил мультиплексор на сдвиговые регистры, но проблема с временными ошибками не решена.

У меня такой глобальный вопрос.
Есь 16 канальный DDC, его данные я записываю с помощью контроллера в память с частотой 200 Мгц. Частота дискретизации данных на выходе DDC 2МГц. Я записываю данные в SDRAm и считываю их.
В этой части проблем с временными ошибками нет.
После принятия порции отсчетов, считанных с памяти, я хочу их обработать в алгоритме подавления несинхронных помех на той же частоте 200 МГц. Но эта частота излишняя, хватает 32 МГц для обработки 1 подавителем отсчетов со всех 16 каналов. И на этой частоте в дизайне появляются временные ошибки.
Как правильно принять эти даннные и обработать? То есть дело не в алгоритме, а в том как правильно обработать данные, принятые на частоте 200 МГц, например, на частоте 100 Мгц, как правильно сделать переход?