Я конечно могу с начала создать проект наново.
Но на сколько я понимаю проект весь описан в скриптовых файлах и дожна быть методика корректировки.
При добавлении модуля в XPS его "видно" при запуске SDK
11:15:45 INFO : Processing command line option -hwspec E:/Halt/maisb_s6/microblaze/SDK/SDK_Export/hw/maisb_s6.xml.
11:15:46 INFO : The hardware specification for project 'microblaze_hw_platform' is different from E:/Halt/maisb_s6/microblaze/SDK/SDK_Export/hw/maisb_s6.xml.
11:15:46 INFO : Copied contents of E:/Halt/maisb_s6/microblaze/SDK/SDK_Export/hw/maisb_s6.xml into \microblaze_hw_platform\system.xml.
11:15:46 INFO : Copied contents of E:\Halt\maisb_s6\microblaze\SDK\SDK_Export\hw\maisb_s6_top.bit into \microblaze_hw_platform\system.bit.
11:15:46 INFO : Copied contents of E:\Halt\maisb_s6\microblaze\SDK\SDK_Export\hw\edkBmmFile_bd.bmm into \microblaze_hw_platform\system_bd.bmm.
11:15:48 INFO : Synchronizing projects in the workspace with the hardware platform specification changes.
11:15:49 INFO : Updating MSS for Board Support Package Project: maisb_2uart_timer_bsp.
The following new driver assignments were made:
Peripheral Instance: rs485, driver: emc_v3_01_a.
11:15:49 INFO : Updating hardware inferred compiler options for maisb_2uart_timer.
11:15:49 INFO : Clearing existing target manager status.Но в файлах проекта изменений не видно.
P.S. Тут
http://www.xilinx.com/tools/xps.htmBenefits of XPS
XPS knowledge of hardware-specific parameters allows it to
guarantee that connectivity is correct and functional
No need to worry about mismatched IO voltages, clocks, etc.
XPS works together with other Xilinx tools to ensure collaborative project planning with PlanAhead,
automated software generation with SDK, simulation with iSim, hardware/software cross trigger debug with ChipScope Pro, design generation with ISE