Cyclone V SoC + DDR3, Подскажите по доступу Опции

[Serb1987]

Добрый день, есть борда с циклоном 5 на борту, нужно получить доступ к памяти, но на этой борде память расположена со стороны процессорного модуля (HPS), а получить доступ нужно из логики, подскажите пожалуйста как лучше поступить или откуда копать необходимую инфу?

[Serb1987]

Блин, проблема на проблеме, теперь с Авалоном... Подскажите будьте добры, почему может не быть сигнала readdatavalid, вернее он все время в 0 и данные с шины не поступают? Waitrequest работает относительно моего read. Пытался изначально читать поэлементтно, потом пробовал бёрстами - не работает.

Код

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity avalon_read is
    generic (hor_res : natural:= 360;
                ver_res : natural:= 288
                );
    port (clk                                     : in std_logic;
            reset                                 : in std_logic;
            fifo_write                            : out std_logic;
            fifo_full                            : in std_logic;
            -- read master
            avm_read_master_read             : out std_logic;
            avm_read_master_address         : out std_logic_vector (29 downto 0);
            avm_read_master_readdata         : in std_logic_vector (31 downto 0);
            avm_read_master_waitrequest     : in std_logic;
            avm_read_readdatavalid         : in std_logic;
            data_out                                : out std_logic_vector (31 downto 0);
            burstcount                            : out std_logic_vector (7 downto 0)
            );
end avalon_read;

architecture Behavioral of avalon_read is

signal pix_cnt        : natural := 0;
signal str_cnt        : natural := 0;
signal quad_cnt    : natural := 0;
signal addr_0        : natural := 0;
signal addr_1        : natural := 0;
signal addr_2        : natural := 0;
signal addr_3        : natural := 0;

signal avm_read    : std_logic := '0';
signal wr_fifo        : std_logic := '0';

-- state machine states
type read_states_T is (idle, running, stopping);----
signal read_state : read_states_T;

-- extra read master signals
signal read_address : natural;         -- the current read address

begin

-------------------------------------------------------------------------------
-- THE READ MASTER STATE MACHINE
-------------------------------------------------------------------------------

read_FSM: process (clk, reset, read_state, avm_read_master_waitrequest)
begin
    if reset = '0' then
        read_state <= idle;
    elsif rising_edge (clk) then----------------------
        case read_state is
            when idle =>
            if fifo_full = '0' and avm_read_readdatavalid = '0' then
                read_state <= running;
                avm_read_master_address <= std_logic_vector(to_unsigned(read_address, 30));
                burstcount <= "00000010";
            else
                read_state <= idle;
            end if;
            when running =>
                if avm_read_master_waitrequest = '0' then
                    read_state <= stopping;

                else
                    read_state <= running;
                end if;
            when stopping =>
--                if avm_read_readdatavalid = '1' then
                    read_state <= idle;
                    if quad_cnt = 3 then
                            quad_cnt <= 0;
                            if pix_cnt = hor_res-1 then
                                pix_cnt <= 0;
                                if str_cnt = ver_res-1 then
                                    str_cnt <= 0;
                                else
                                    str_cnt <= str_cnt+1;
                                end if;
                            else
                                pix_cnt <= pix_cnt +1;
                            end if;
                        else
                            quad_cnt <= quad_cnt+1;
                        end if;
--                else
--                    read_state <= stopping;
--                end if;
        end case;
    end if;
end process;



process(clk, reset, fifo_full, read_state, quad_cnt, avm_read_master_waitrequest)
begin
if reset = '0' then
        fifo_write <= '0';
elsif falling_edge(clk) then
    if (quad_cnt = 3 and read_state = running and fifo_full = '0' and avm_read_master_waitrequest = '0')  then ---- avm_read_readdatavalid = '1'
        fifo_write <= '1';
    else
        fifo_write <= '0';
    end if;
end if;
end process;

addr_0 <= (pix_cnt*2 + str_cnt*2*(hor_res*2))*4;--+ 500000000
addr_1 <= (pix_cnt*2+1 + str_cnt*2*(hor_res*2))*4;
addr_2 <= (pix_cnt*2 + (str_cnt*2+1)*(hor_res*2))*4;
addr_3 <= (pix_cnt*2+1 + (str_cnt*2+1)*(hor_res*2))*4;

read_address <= addr_0 when quad_cnt = 0 else
                     addr_1 when quad_cnt = 1 else
                     addr_2 when quad_cnt = 2 else
                     addr_3 when quad_cnt = 3;

data_out(31 downto 24) <= avm_read_master_readdata(15 downto 8) when quad_cnt = 0;---UL
data_out(23 downto 16) <= avm_read_master_readdata(15 downto 8) when quad_cnt = 1;---UR
data_out(15 downto 8) <= avm_read_master_readdata(15 downto 8) when quad_cnt = 2;----LL
data_out(7 downto 0) <= avm_read_master_readdata(15 downto 8) when quad_cnt = 3;-----LR
        
avm_read_master_read <= '1' when read_state = running and fifo_full = '0' else '0';

end Behavioral;

Сообщение отредактировал Serb1987 - Jul 17 2014, 09:25