Внешние прерывания, STM32F103VB Опции

[Jenya7]

Я пытаюсь включить внешние прерывания в свою программу на STM32F103VB.

CODE

void ExtIntInit(void)
{
// enable clock for Alternate Function
RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;

//BUT - PE0
GPIOE->CRL &= ~GPIO_CRL_MODE0; //Configure as input
GPIOE->CRL &= ~GPIO_CRL_CNF0;
GPIOE->CRL |= GPIO_CRL_CNF0_1; //input with pull-up/pull-down resistor
GPIOE->BSRR |= GPIO_BSRR_BS0; //set pull-up
//ENC1 - PE1
GPIOE->CRL &= ~GPIO_CRL_MODE1; //Configure as input
GPIOE->CRL &= ~GPIO_CRL_CNF1;
GPIOE->CRL |= GPIO_CRL_CNF1_1; //input with pull-up/pull-down resistor
GPIOE->BSRR |= GPIO_BSRR_BS1; //set pull-up
//ENC2 - PE2
GPIOE->CRL &= ~GPIO_CRL_MODE2; //Configure as input
GPIOE->CRL &= ~GPIO_CRL_CNF2;
GPIOE->CRL |= GPIO_CRL_CNF2_1; //input with pull-up/pull-down resistor
GPIOE->BSRR |= GPIO_BSRR_BS2; //set pull-up

//interrupt source PE
AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI0_PE; //PE0 - BUT
AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI1_PE; //PE1 - ENC1
AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI2_PE; //PE2 - ENC2
AFIO->EXTICR[0] |= AFIO_EXTICR1_EXTI3_PE; //PE3 - ENC3

//interrupt edge
EXTI->RTSR |= 0; //EXTI_RTSR_TR0; //rising
EXTI->FTSR |= EXTI_FTSR_TR0; //falling
EXTI->FTSR |= EXTI_FTSR_TR1; //falling
EXTI->FTSR |= EXTI_FTSR_TR2; //falling
EXTI->FTSR |= EXTI_FTSR_TR3; //falling

//enable ext interrupt
EXTI->IMR |= EXTI_IMR_MR0;
EXTI->IMR |= EXTI_IMR_MR1;
EXTI->IMR |= EXTI_IMR_MR2;
EXTI->IMR |= EXTI_IMR_MR3;

NVIC_EnableIRQ(EXTI0_IRQn);
NVIC_EnableIRQ(EXTI1_IRQn);
NVIC_EnableIRQ(EXTI2_IRQn);
NVIC_EnableIRQ(EXTI3_IRQn);
}

И обработчик

CODE

void EXTI0_IRQHandler(void) //button pressed
{
EXTI->PR = EXTI_PR_PR0; //clear flag???
TIM4->CNT = 0;
TIM4->CR1 |= TIM_CR1_CEN;
//but_int = true;
//NVIC_EnableIRQ(TIM7_IRQn);

}
void EXTI1_IRQHandler(void) //encoder1
{
EXTI->PR = EXTI_PR_PR1; //clear flag???
enc1_int = 1;
if(DIR1)
{ mot1_position++; }
else
{
if(mot1_position > 0)
{ mot1_position--; }
}
}

void EXTI2_IRQHandler(void) //encoder2
{
EXTI->PR = EXTI_PR_PR2; //clear flag???
if(DIR2)
{ mot2_position++; }
else
{
if(mot2_position > 0)
{ mot2_position--; }
}
}

void EXTI3_IRQHandler(void) //encoder3
{

EXTI->PR = EXTI_PR_PR3; //clear flag???
if(DIR3)
{ mot3_position++; }
else
{
if(mot3_position > 0)
{ mot3_position--; }
}
}

До этого кода все работает нормально. После включения этого куска кода камень умирает и не реагирует ни на что. Я уже пару дней бьюсь над проблемой. Читаю документацию вдоль и поперек не могу понять где проблема.

[Golikov A.]

Огромный бонус ПЛИС - это возможность создание реально параллельных блоков, а еще в добавок там куча памяти теперь и прочих радостей. Можно и проц запихать, отказавшись от внешнего. Для частной маленькой задачи обработки энкодеров можно взять малюсенькую CPLD.

Я вот тут пытался представить как обработать энкодер на таймере, у меня не получилось 4 электронных отсчетов на реальную линию, и направление надо учитывать, а в ПЛИС все будет четко, 4 электронных отсчета на реальный, и регистры накопления внутри ПЛИС.

да еще забыл

spi_clk - вот этот сигнал лучше завести на клоковый вход ПЛИС (это спец ножки, их много). Можно и на обычный, но времянка просядет, на клоковый лучше.

И я вам настоятельно рекомендую пересаживаться на Verilog, я начинал с VHDL, а теперь на верилог пересел, одни положительные эмоции

во я еще тестбенч нашел от модуля

CODE

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:18:31 04/16/2014
// Design Name: SPIComModule_v4_00
// Module Name: E:/SYNC_MOTOR/FPGA/SPIComModule_v4_00_tb.v
// Project Name: SyncMotor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: SPIComModule_v4_00
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////

module SPIComModule_v4_00_tb;
localparam DATA_SIZE = 16;

// Inputs
reg clk;
reg spi_cs;
reg spi_clk;
reg spi_in;
reg [DATA_SIZE - 1 : 0] data_from_module;
reg wr_rd_sync;
reg wr_ack;
reg rd_ack;

// Outputs
wire spi_out;
wire [15:0] module_sel;
wire [7:0] submodule_sel;
wire [DATA_SIZE - 1 : 0] data_to_module;
wire wr_strb;
wire rd_strb;
wire check_sum_ok;
wire data_write_done;
wire data_rdy;

reg [DATA_SIZE - 1 : 0] datareg_00;
reg [DATA_SIZE - 1 : 0] datareg_01;
reg [DATA_SIZE - 1 : 0] datareg_10;
reg [DATA_SIZE - 1 : 0] datareg_11;

reg [DATA_SIZE - 1 : 0] data ;
reg [7 : 0] addr ;
reg [7 : 0] check_sum;

// Instantiate the Unit Under Test (UUT)
SPIComModule_v4_00
#(.MODULE_DATA_SIZE(DATA_SIZE)
)
uut
(
.clk(clk),
.spi_cs(spi_cs),
.spi_clk(spi_clk),
.spi_in(spi_in),
.spi_out(spi_out),
.module_sel(module_sel),
.submodule_sel(submodule_sel),
.data_to_module(data_to_module),
.data_from_module(data_from_module),
.wr_rd_sync(wr_rd_sync),
.wr_strb(wr_strb),
.wr_ack(wr_ack),
.rd_strb(rd_strb),
.rd_ack(rd_ack),
.check_sum_ok(check_sum_ok),
.data_write_done(data_write_done),
.data_rdy(data_rdy)
);

integer i;

initial begin
// Initialize Inputs
spi_cs = 0;
spi_clk = 0;
spi_in = 0;
wr_rd_sync = 0;
data = 0;
addr = 0;
check_sum = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here
spi_cs <= 1;
spi_clk <= 1;

#100;


//-----------------------------------------------------------
data = 16'h0000;
addr = 8'b10010001;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 0;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;
wr_rd_sync = 1;
#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------






//-----------------------------------------------------------
#50;
data = 16'hAABB;
addr = 8'b00001001;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 1;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------




//-----------------------------------------------------------
#50;
data = 16'hCCDD;
addr = 8'b00010010;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 1;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------


//-----------------------------------------------------------
#50;
data = 16'hAABB;
addr = 8'b10001001;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 1;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------

//-----------------------------------------------------------
#50;
data = 16'hAABB;
addr = 8'b10010010;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 1;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------



//-----------------------------------------------------------
#50;
data = 16'hEEFF;
addr = 8'b00000000;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 1;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------

//-----------------------------------------------------------
#50;
data = 16'h0000;
addr = 8'b10000000;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 1;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------


#1000;



//-----------------------------------------------------------
#50;
data = 16'hCCCC;
addr = 8'b10010010;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 0;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------



//-----------------------------------------------------------
#50;
data = 16'hCCCC;
addr = 8'b00000000;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 0;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------

//-----------------------------------------------------------
#50;
data = 16'h0000;
addr = 8'b10000000;
check_sum = 8'hFF + data[7:0] + data[15:8] + addr;
check_sum = 0 - check_sum;

wr_rd_sync = 0;
spi_cs <= 0;

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = addr[7-i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = data[DATA_SIZE - 1 -i];
#2;
spi_clk = 1;
#10;
end

for (i=0;i<8;i=i+1)
begin
spi_clk = 0;
#8;
spi_in = check_sum[7-i];
#2;
spi_clk = 1;
#10;
end

#100;

if(data_rdy == 1)
for (i=0;i<DATA_SIZE;i=i+1)
begin
spi_clk = 0;
#10;
spi_clk = 1;
#10;
end

spi_cs <= 1;
//-----------------------------------------------------------

end


initial begin
// Initialize Inputs
clk = 0;

// Wait 100 ns for global reset to finish
#98;

// Add stimulus here
forever begin
#5;
clk <= ~clk;
end

end

initial begin
// Initialize Inputs
datareg_00 = 0;
datareg_01 = 0;
datareg_10 = 0;
datareg_11 = 0;
wr_ack = 0;
rd_ack = 0;
data_from_module = 0;

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here
forever begin
#1;
wr_ack <= 0;
rd_ack <= 0;
data_from_module <= 'hFFFF;

if((module_sel == 2'b1)&&(submodule_sel == 2'b1))
begin
if(wr_strb == 1)
begin
datareg_00 <= data_to_module;
wr_ack <= 1;
end
if(rd_strb == 1)
begin
data_from_module <= datareg_00;
rd_ack <= 1;
end
end

if((module_sel == 2'b10)&&(submodule_sel == 2'b1))
begin
if(wr_strb == 1)
begin
datareg_10 <= data_to_module;
wr_ack <= 1;
end
if(rd_strb == 1)
begin
data_from_module <= datareg_10;
rd_ack <= 1;
end
end


if((module_sel == 2'b1)&&(submodule_sel == 2'b10))
begin
if(wr_strb == 1)
begin
datareg_01 <= data_to_module;
wr_ack <= 1;
end
if(rd_strb == 1)
begin
data_from_module <= datareg_01;
rd_ack <= 1;
end
end

if((module_sel == 2'b10)&&(submodule_sel == 2'b10))
begin
if(wr_strb == 1)
begin
datareg_11 <= data_to_module;
wr_ack <= 1;
end
if(rd_strb == 1)
begin
data_from_module <= datareg_11;
rd_ack <= 1;
end
end

end

end


endmodule