Почему зависает компьютер?, При отладке PCI-платы в ДОСе Опции

[Гвоздик]

Здраствуйте. Пытаюсь отладить ведомое устройство (target) на PCI-шине (33 МГц), после прочтения форума по этой теме нарочно приобрел старую материнскую плату на Пентиуме 100, чтобы не отключались клоки на шине для устройства без конфигурации (клоки действительно идут - проверяю через ЖКИ), однако при посылке данных в порт 0х200 (адрес моей платы) компьютер зависает намертво после первой же передачи данных в порт. Гружусь с дисковода с дискеты в ДОС. Отладочная плата Max2 Development kit, исходные тексты прилагаю (для ПЛИС и отсылочную программу для ДОСа). В чем может быть дело? Почитал на www.fpga4fun.com, что можно и без конфигурации по-простому гонять данные через PCI. Почему не выходит, эх кабы знать...

Код

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pci_target is
  generic(AD_PCI_BUS_WIDTH : natural := 31;
    C_BE_WIDTH : natural := 3;
    VALID_CARD_DATA_WIDTH : natural := 7;
    CARD_ADDRESS : natural := 512; -- 0x200
    C_BE_WRITE_COMMAND : natural := 3);
  port(RSTn : in std_logic;
    CLK : in std_logic;
    AD : in std_logic_vector(AD_PCI_BUS_WIDTH downto 0);
    FRAMEn : in std_logic;
    C_BEn : in std_logic_vector(C_BE_WIDTH downto 0);
    IRDYn : in std_logic;
    TRDYn : out std_logic;
    DEVSELn : out std_logic;
    valid_card_data : out std_logic_vector(VALID_CARD_DATA_WIDTH downto 0);
    BUS_ENABLEn : out std_logic;
    test_led : out std_logic);
end entity pci_target;

architecture behavioural of pci_target is
signal devsel_sig_n : std_logic := 'Z';
signal trdy_sig_n : std_logic := 'Z';
signal card_address_found : std_logic := '0';
signal valid_card_data_sig : std_logic_vector(VALID_CARD_DATA_WIDTH downto 0) := X"00";
signal test_led_sig : std_logic := '1';
begin
  process(RSTn, CLK, FRAMEn, AD(AD_PCI_BUS_WIDTH downto 0))
  begin
    if (RSTn = '0') then
      devsel_sig_n <= 'Z';
      trdy_sig_n <= 'Z';
      card_address_found <= '0';
      valid_card_data_sig <= X"00";
      test_led_sig <= '1';
    else
      if (CLK'event and CLK = '1') then
        test_led_sig <= '0';
        if (FRAMEn = '0') then
          if (IRDYn = '1') then
            trdy_sig_n <= 'Z';
            if ((AD(AD_PCI_BUS_WIDTH downto 0) = CARD_ADDRESS) and (C_BEn(C_BE_WIDTH downto 0) = C_BE_WRITE_COMMAND)) then
              card_address_found <= '1';
              devsel_sig_n <= '0';
            else
              card_address_found <= '0';
              devsel_sig_n <= 'Z';
            end if;
          else
            if ((card_address_found = '1') and (C_BEn(0) = '0')) then
              valid_card_data_sig(VALID_CARD_DATA_WIDTH downto 0) <= AD(VALID_CARD_DATA_WIDTH downto 0);
              trdy_sig_n <= '0';
              devsel_sig_n <= '0';
            else
              trdy_sig_n <= 'Z';
              devsel_sig_n <= 'Z';
            end if;
          end if;
        else
          devsel_sig_n <= 'Z';
          trdy_sig_n <= 'Z';
          card_address_found <= '0';
        end if;
      end if;
    end if;
  end process;

  valid_card_data(VALID_CARD_DATA_WIDTH downto 0) <= valid_card_data_sig(VALID_CARD_DATA_WIDTH downto 0);
  DEVSELn <= devsel_sig_n;
  TRDYn <= trdy_sig_n;
  BUS_ENABLEn <= '0'; -- enable bus formers for 5V pci
  test_led <= test_led_sig;

end architecture behavioural;

и досовский исходник еще:

Код

#include <stdio.h>
#include <dos.h>
int main(void)
{
  int port = 0x200;
  unsigned char lcd_text[16] = {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,
    0x38,0x39,0x41,0x42,0x43,0x44,0x45,0x46};
  unsigned char i = 0;
  clrscr();
  printf("Output scan codes to the port: %d in endless cycle...\n",port);
  for (i = 0; i < 16; i++)
  {
    outportb(port, lcd_text[i]);
    printf("To the port %d was sent data %d\n",port, lcd_text[i]);
  }
  printf("\n");
  for (i = 0; i < 16; i++)
  {
    outp(port, (int)lcd_text[i]);
    printf("Second output to the port %d and data = %d", port, lcd_text[i]);
  }
  return 0;
}

[Гвоздик]

Привожу исходные тексты модулей ведомого на шине PCI:

Код

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pci_target is
  generic(AD_PCI_BUS_WIDTH : natural := 31;
    C_BE_WIDTH : natural := 3;
    VALID_SYMBOL_CODE_WIDTH : natural := 7;
    VALID_SYMBOL_POSITION_WIDTH : natural := 12;
    CARD_ADDRESS : natural := 512; -- 0x200
    C_BE_WRITE_COMMAND : natural := 3;
    LCD_POSITION_WIDTH : natural := 4);
  port(RSTn : in std_logic;
    CLK : in std_logic;
    AD : in std_logic_vector(AD_PCI_BUS_WIDTH downto 0);
    FRAMEn : in std_logic;
    C_BEn : in std_logic_vector(C_BE_WIDTH downto 0);
    IRDYn : in std_logic;
    TRDYn : inout std_logic;
    DEVSELn : inout std_logic;
    VALID_SYMBOL_CODE : out std_logic_vector(VALID_SYMBOL_CODE_WIDTH downto 0);
    BUS_ENABLEn : out std_logic;
    LCD_SYMBOL_POSITION : out std_logic_vector(LCD_POSITION_WIDTH downto 0);
    TEST_LED : out std_logic_vector(3 downto 0));
end entity pci_target;

architecture behavioural of pci_target is

constant SpaceSymbolCode : std_logic_vector(VALID_SYMBOL_CODE_WIDTH downto 0) := X"20";
signal Transaction, TransactionStart, TransactionEnd, Targeted, LastDataTransfer, DevSelOE, DevSel, DataTransfer : std_logic;
signal ValidLcdSymbolCode : std_logic_vector(VALID_SYMBOL_CODE_WIDTH downto 0) := X"00";
signal ValidLcdSymbolPositionSignal : std_logic_vector(LCD_POSITION_WIDTH downto 0) := "11111";
signal TestLedSignal : std_logic_vector(3 downto 0) := X"F";

begin
  process(RSTn, CLK)
  begin
    if (RSTn = '0') then
      Transaction <= '0';
      DevSelOE <= '0';
      DevSel <= '0';
      ValidLcdSymbolPositionSignal <= "00000";
      ValidLcdSymbolCode <= SpaceSymbolCode;
    else
      if (CLK'event and CLK = '1') then
        if (Transaction = '0') then
          Transaction <= TransactionStart;
          DevSelOE <= Targeted;
          DevSel <= Targeted;
        else
          Transaction <= not TransactionEnd;
          if (TransactionEnd = '1') then
            DevSelOE <= '0';
          end if;
          DevSel <= DevSel and (not LastDataTransfer);
        end if;
        if (DataTransfer = '1') then
          ValidLcdSymbolCode(VALID_SYMBOL_CODE_WIDTH downto 0) <= AD(VALID_SYMBOL_CODE_WIDTH downto 0);
          ValidLcdSymbolPositionSignal(LCD_POSITION_WIDTH downto 0) <= AD(VALID_SYMBOL_POSITION_WIDTH downto (VALID_SYMBOL_CODE_WIDTH + 1));
          TestLedSignal <= not ValidLcdSymbolPositionSignal(3 downto 0);
        end if;
      end if;
    end if;
  end process;

  process(TransactionStart, AD(AD_PCI_BUS_WIDTH downto 0), C_BEn(C_BE_WIDTH downto 0))
  begin
    if ((AD(AD_PCI_BUS_WIDTH downto 0) = CARD_ADDRESS) and (C_BEn(C_BE_WIDTH downto 0) = C_BE_WRITE_COMMAND)) then
      Targeted <= TransactionStart;
    else
      Targeted <= '0';
    end if;
  end process;

  process(DevSelOE, DevSel)
  begin
    if (DevSelOE = '1') then
      DEVSELn <= not DevSel;
      TRDYn <= not DevSel;
    else
      DEVSELn <= 'Z';
      TRDYn <= 'Z';
    end if;
  end process;

  TransactionStart <= (not Transaction) and (not FRAMEn);
  TransactionEnd <= Transaction and FRAMEn and IRDYn;
  LastDataTransfer <= FRAMEn and (not IRDYn) and (not TRDYn);
  DataTransfer <= DevSel and (not IRDYn) and (not TRDYn);

  BUS_ENABLEn <= '0'; -- enable bus formers for 5V pci
  VALID_SYMBOL_CODE(VALID_SYMBOL_CODE_WIDTH downto 0) <= ValidLcdSymbolCode(VALID_SYMBOL_CODE_WIDTH downto 0);
  LCD_SYMBOL_POSITION(LCD_POSITION_WIDTH downto 0) <= ValidLcdSymbolPositionSignal(LCD_POSITION_WIDTH downto 0);
  TEST_LED <= TestLedSignal;

end architecture behavioural;