DDR2+Cyclone3 - не пролазят констрейны, ищется способ побороть... Опции

[alexPec]

Всем доброго дня. Собрал в Q11 сопц, собственно процессор + DDR2 контроллер + ethernet. Чип EP3C25 память - MT47H64M16-25Е. В настройках контроллера все частоты выше 266МГЦ (стояло 400мгц) поставил 300 МГц. Частота памяти 150 МГц. В итоге имею слэки отрицательные. Смотрю в клоки - там откуда-то берется 198.05МГц. В настройках нет такого вообще. Мне столько и не надо, достаточно 150МГц. Слэк -1.2хх нс, если период был бы не 5нс, а 6,66 (для 150МГц), то вроде все должно сойтись. Подскажите пожалуйста куда копать и как ему объяснить, что не надо мне 200, хватает 150 МГц?
Отчет таймквеста при компиляции прилагаю.

Заранее благодарен.

Прикрепленные файлы

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[krux]

assignments -> device -> device and pin options -> pin options
ввести вручную сколько надо

[alexPec]

assignments -> device -> device and pin options -> pin options
ввести вручную сколько надо

Чет не спасает:

Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Error (169015): Cannot place pin ddr_dq[8] to location B12
Error (169223): Can't place VREF pin C11 (VREFGROUP_B7_N0) for pin ddr_dq[8] of type bi-directional with SSTL-18 Class I I/O standard at location B12
Error (169224): Too many output and bidirectional pins per VCCIO and ground pair in I/O bank 7 when the VREF pin C11 (VREFGROUP_B7_N0) is used on device EP3C25F256I7 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out
Info (169220): Location D11 (pad PAD_177): Pin ddr_ba[2] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location D12 (pad PAD_178): Pin ddr_ba[1] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location A13 (pad PAD_179): Pin ddr_ba[0] of type output uses SSTL-18 Class I I/O standard
Info (169225): Following 5 pins have the same output enable group 1: 3 pins require VREF pin and 5 pins could be output
Info (169220): Location B13 (pad PAD_180): Pin ddr_dq[15] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location E11 (pad PAD_183): Pin ddr_a[0] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location E10 (pad PAD_184): Pin ddr_a[2] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location A12 (pad PAD_186): Pin ddr_dq[14] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location A11 (pad PAD_188): Pin ddr_dq[9] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location A14 (pad PAD_181): Pin ddr_clk_n of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location B14 (pad PAD_182): Pin ddr_clk of type bi-directional uses SSTL-18 Class I I/O standard
Info (169222): Following 12 location(s) shared the same VCCIO and ground pair, and 10 pin(s) are placed
Info (169220): Location D11 (pad PAD_177): Pin ddr_ba[2] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location D12 (pad PAD_178): Pin ddr_ba[1] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location A13 (pad PAD_179): Pin ddr_ba[0] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location B13 (pad PAD_180): Pin ddr_dq[15] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location A14 (pad PAD_181): Pin ddr_clk_n of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location B14 (pad PAD_182): Pin ddr_clk of type bi-directional uses SSTL-18 Class I I/O standard
Info (169220): Location E11 (pad PAD_183): Pin ddr_a[0] of type output uses SSTL-18 Class I I/O standard
Info (169220): Location E10 (pad PAD_184): Pin ddr_a[2] of type output uses SSTL-18 Class I I/O standard
Info (169221): Location (pad PAD_185): unused
Info (169220): Location A12 (pad PAD_186): Pin ddr_dq[14] of type bi-directional uses SSTL-18 Class I I/O standard
Info (169221): Location B12 (pad PAD_187): unused (but has pin assignment of ddr_dq[8])
Info (169220): Location A11 (pad PAD_188): Pin ddr_dq[9] of type bi-directional uses SSTL-18 Class I I/O standard
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
Error (171000): Can't fit design in device
Warning (169082): Design uses current of 400.0 mA for 15 consecutive horizontal output pads in an I/O bank -- Altera recommends a maximum current of 240.0 mA for any 14 consecutive output pads in an I/O bank
Warning (169082): Design uses current of 400.0 mA for 15 consecutive vertical output pads in an I/O bank -- Altera recommends a maximum current of 240.0 mA for any 12 consecutive output pads in an I/O bank
Warning (169180): Following 1 pins must use external clamping diodes.
Info (169178): Pin epcs_sdi uses I/O standard 2.5 V at H2
Warning (169064): Following 2 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
Info (169065): Pin ddr_clk has a permanently enabled output enable
Info (169065): Pin ddr_clk_n has a permanently enabled output enable
Error: Quartus II 32-bit Fitter was unsuccessful. 4 errors, 21 warnings
Error: Peak virtual memory: 326 megabytes
Error: Processing ended: Fri Oct 03 01:00:40 2014
Error: Elapsed time: 00:00:25
Error: Total CPU time (on all processors): 00:00:23

Я уж и в output enable group затолкнул все ddr-сигналы. Что еще можно сделать?
UPD ничего не понимаю: вешаю сигнал с пина B11 на D14 и ошибка уходит. В том же банке, в той же Vref группе, но плату то в этом случае переделывать ...
Неужто тупик?