Ethernet на ПЛИС, PHY+MAC+UDP/IP Опции

[Alexey_pashinov]

Собрал проект, реализующий Ethernet (PHY+MAC+UDP/IP). Я формирую на ПЛИС'ке данные, которые хочу подать, на UDP. При отвправке самого первого пакета при выставлении сигнала sof, UDP/IP stack формирует arp запрос получателю, далее приходит отправителю ответ и после UDP/IP выствляет сигнал dst_rdy, который говорит о том что блок UDP/IP готов к приему данных для отправки. При передаче остальных пакетов сигнал dst_rdy выставляется почти сразу же после выставления sof (промежуток времени между их выставлением равен длине формируемого заголовка). Проблема заключается в следующем. При отправке самого первого пакета сигнал dst_rdy выставляется не сразу, может выставиться аж через 3-5 мин, может меньше может больше, а может и не выставиться. Но после того как это произошло (установилось видимо связь) дальнейшая передача пакетов происходит исправно. Кстати проблема возникает не всегда, например когда проверяю работу на 100 Мбит, зачастую передача работает и редко такое возникает, а когда проверяю на 1gb то наоборот зачастую не работает и только редко начинает работать сразу. Помогите разобраться с этим, буду очень признателен).

Могу выложить описание автомата формир отправку и диаграммы

[HFSE]

Всем сапсибо за советы.
Но до сих пор я не вижу пакетов в wireshark.
Вот как я это делал:
1. Сначало вбил данные в генератор пакетов
2. Сгенерировал пакет
3. Залил VHDL код в FPGA -> wireshark ничего не показывает, НО ...
При просмотре Interface Details обнаружил что пакеты приходят, но они все с ошибками.
Что я не так посылаю, или точней как послать правильно?
Зарание благодарен.

CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fsm is
Port (
RESET : in STD_LOGIC;
CLK_IN : in STD_LOGIC;
CLK_IN_90 : in STD_LOGIC;
LINK_EN : in STD_LOGIC;
TX_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
TX_ERR_OUT : out STD_LOGIC;
TX_EN_OUT : out STD_LOGIC;
TX_CLK_OUT : out STD_LOGIC
);
end fsm;

architecture Behavioral of fsm is

type FSM_STATE is ( A1, A2, A3, A4, A5, A6, A7, A8, A9, A10,
A11, A12, A13, A14, A15, A16, A17, A18, A19, A20,
A21, A211, A222, A22, A23, A24, A25, A26, A27, A28, A29, A30,
A31, A32, A33, A34, A35, A36, A37, A38, A39, A40,
A41, A42, A43, A44, A45, A46, A47, A48, A49, A50,
A51, A52, A53, A54, A55, A56, A57, A58, A59, A60,
A61, A62, A63, A64, A65, A66, A67, A68, A69, A70,
A71, A72, A73, A74, A75, A76, A77, A78, A79, A80,
A81, A82, A83, A84, A85, A86, A87, A88, A89, A90,
A91, A92, A93, A94, A95, A96, A97, A98, A99
);

signal STATE : FSM_STATE := A1;
signal NEXT_STATE : FSM_STATE;
signal COUNTER_1 : integer range 0 to 100000 := 0;

signal data_buffer : std_logic_vector(7 downto 0) := x"00";

begin

Z : process(RESET, CLK_IN, LINK_EN)
begin

if (RESET = '0') then
STATE <= A1;
elsif (rising_edge(CLK_IN)) then
if (LINK_EN = '0') then
STATE <= NEXT_STATE;
else
STATE <= A1;
end if;
end if;

end process Z;

TX_DATA_OUT <= data_buffer;

FSM_PROC: process (STATE, CLK_IN, CLK_IN_90)
begin
case STATE is
-- Preable
when A1 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= '0'; NEXT_STATE <= A2;
when A2 => data_buffer <= x"55"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A3;
when A3 => data_buffer <= x"55"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A4;
when A4 => data_buffer <= x"55"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A5;
when A5 => data_buffer <= x"55"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A6;
when A6 => data_buffer <= x"55"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A7;
when A7 => data_buffer <= x"55"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A8;
when A8 => data_buffer <= x"55"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A9;
when A9 => data_buffer <= x"D5"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A10;
-- MAC Destination
when A10 => data_buffer <= x"FF"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A11;
when A11 => data_buffer <= x"FF"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A12;
when A12 => data_buffer <= x"FF"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A13;
when A13 => data_buffer <= x"FF"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A14;
when A14 => data_buffer <= x"FF"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A15;
when A15 => data_buffer <= x"FF"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A16;
--MAC Source
when A16 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A17;
when A17 => data_buffer <= x"12"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A18;
when A18 => data_buffer <= x"34"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A19;
when A19 => data_buffer <= x"56"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A20;
when A20 => data_buffer <= x"78"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A21;
when A21 => data_buffer <= x"90"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A211;
-- Ethernet Typ <=> IP
when A211 => data_buffer <= x"08"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A222;
when A222 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A22;
-- IP Header
when A22 => data_buffer <= x"45"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A23; -- Version + IHL
when A23 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A24; -- TOS
when A24 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A25; -- Total Lengh
when A25 => data_buffer <= x"30"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A26; -- Total Lengh
when A26 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A27; -- Identification
when A27 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A28; -- Identification
when A28 => data_buffer <= x"01"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A29; -- Flags
when A29 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A30; -- Fragment offset
when A30 => data_buffer <= x"80"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A31; -- TTL
when A31 => data_buffer <= x"11"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A32; -- Protocol <=> UDP
-- IP Header Check Sum = IP Header + IP Source + IP Destin in Format x"0000"
when A32 => data_buffer <= x"A3"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A33;
when A33 => data_buffer <= x"B8"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A34;
--IP Source
when A34 => data_buffer <= x"C0"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A35;
when A35 => data_buffer <= x"FF"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A36;
when A36 => data_buffer <= x"0A"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A37;
when A37 => data_buffer <= x"01"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A38;
-- IP Dest
when A38 => data_buffer <= x"C0"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A39;
when A39 => data_buffer <= x"FF"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A40;
when A40 => data_buffer <= x"0A"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A41;
when A41 => data_buffer <= x"05"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A42;
--Port Source
when A42 => data_buffer <= x"13"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A43;
when A43 => data_buffer <= x"88"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A44;
-- Port Dest
when A44 => data_buffer <= x"13"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A45;
when A45 => data_buffer <= x"88"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A46;
-- UDP Lengh Payload = Port Source + Port Dest + Lengh Payload + UDP Checksum + Payload <=> 26
when A46 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A47;
when A47 => data_buffer <= x"1C"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A48;
-- UDP Checksum
when A48 => data_buffer <= x"CA"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A49;
when A49 => data_buffer <= x"1E"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A50;
-- UDP Payload
when A50 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A51;
when A51 => data_buffer <= x"01"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A52;
when A52 => data_buffer <= x"02"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A53;
when A53 => data_buffer <= x"03"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A54;
when A54 => data_buffer <= x"04"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A55;
when A55 => data_buffer <= x"05"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A56;
when A56 => data_buffer <= x"06"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A57;
when A57 => data_buffer <= x"07"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A58;
when A58 => data_buffer <= x"08"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A59;
when A59 => data_buffer <= x"09"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A60;
when A60 => data_buffer <= x"10"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A61;
when A61 => data_buffer <= x"11"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A62;
when A62 => data_buffer <= x"12"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A63;
when A63 => data_buffer <= x"13"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A64;
when A64 => data_buffer <= x"14"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A65;
when A65 => data_buffer <= x"15"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A66;
when A66 => data_buffer <= x"16"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A67;
when A67 => data_buffer <= x"17"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A68;
when A68 => data_buffer <= x"18"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A69;
when A69 => data_buffer <= x"19"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A70;
-- CRC32 Checksum
when A70 => data_buffer <= x"82"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A71; -- 82
when A71 => data_buffer <= x"0A"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A72; -- 0A
when A72 => data_buffer <= x"C9"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A73; -- C9
when A73 => data_buffer <= x"C2"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '1'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A74; -- C2

when A74 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A75;
when A75 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A76;
when A76 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A77;
when A77 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A78;
when A78 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A79;
when A79 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A80;
when A80 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A81;
when A81 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A82;
when A82 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A83;
when A83 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A84;
when A84 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A85;
when A85 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A86;
when A86 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A87;
when A87 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A88;
when A88 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A89;
when A89 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A90;
when A90 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A91;
when A91 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A92;
when A92 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A93;
when A93 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= CLK_IN_90; NEXT_STATE <= A94;
when A94 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= '0'; NEXT_STATE <= A95;
when A95 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= '0'; NEXT_STATE <= A96;
when A96 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= '0'; NEXT_STATE <= A97;
when A97 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= '0';

if rising_edge(CLK_IN) then
if (COUNTER_1 = 100000) then
COUNTER_1 <= 0;
NEXT_STATE <= A98;
else
COUNTER_1 <= COUNTER_1 + 1;
end if;
end if;

when A98 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= '0'; NEXT_STATE <= A99;
when A99 => data_buffer <= x"00"; TX_ERR_OUT <= '0'; TX_EN_OUT <= '0'; TX_CLK_OUT <= '0'; NEXT_STATE <= A1;



when others => NEXT_STATE <= A1;

end case;

end process FSM_PROC;
end Behavioral;

Сообщение отредактировал des00 - Jun 22 2015, 14:19

Причина редактирования: используйте теги codebox для оформления больших сегментов кода (с) модератор

Эскизы прикрепленных изображений

 

[Sergey_Bekrenyov]

А зачем Вы TX_CLK_OUT в ноль опускаете? PHY не сможет линк установить, так и будет туда-сюда дергаться

FSM_PROC: process (STATE, CLK_IN, CLK_IN_90) - частоты уберите из списка чувствительности

[HFSE]

А зачем Вы TX_CLK_OUT в ноль опускаете? PHY не сможет линк установить, так и будет туда-сюда дергаться

FSM_PROC: process (STATE, CLK_IN, CLK_IN_90) - частоты уберите из списка чувствительности

Добрый день, Сергей.
Спасибо большое за совет , все заработало.
Проблема действительно была с клоком.