Со схематикой и моделированием вроде как понятно, имелось в виду по популярности, дизайн довольно таки отличается в зависимости (padstaks, корпуса, futpints, layers ...) или хотя многое зависит от клиента, но все же, было бы неплохо покурить эту тему по конкретной специфике.
По Вашему мнению, на чем нужно акцентировать процесс обучения, исходя, к примеру из н.у. описаний клиентов:
• Responsible for all aspect of IC mask design, include floor-planning, physical synthesis, clocktree synthesis, IR drop , LP analysis flow techniques and parasitic extraction in deep sub microns
• Implementation of Low power layout methodology with multiple power domain and power switches.
• Execution of Static and dynamic power analysis using Redhawk
• Perform , Static timing analysis to handle complex timing closure.
• Review of constraints of data-paths and all physical verification.
• Work with other design engineer in Synthesis, Design for Testability, STA/timing closure and Equivalent checks to resolve issues.
The group you will join is in charge of developing the CORE of Intel’s next generation Wireless products, taking part in all design phases.
The group makes use of state of the art VLSI design tools, while meeting very challenging timelines, quality, low power, and area and speed constraints.
You will be in charge of a cutting edge High Speed digital design of various blocks in the RF domain...
As a RF & Analog Physical design engineer, you will be leading your team`s projects and will have the autonomy to create bottoms-up elements of chip design.
You will use phases of physical design development, including parasitic extraction, static timing, wire load models, clock generation, custom polygon editing, floor planning, full-chip assembly, packaging, and verification.
You will troubleshoot design issues and apply proactive intervention.
Заинтересован в предложениях относительно удаленного обучения, писать в личку
Сообщение отредактировал Magnet - Jun 24 2016, 09:07
Ликбез
Jun 20 2016, 10:10
