Попробуй это - мне помогло 0- I´ve changed the data and address vectors of my WB core to adapt it to the 32 buses of the wrapper 1- Download the wrapper from opencores 2 - Copy the wrapper files to pcores directory 3- Change the bbd file to ################################################################################ ## ## Copyright © 2000-2004 ASICS World Services, LTD. ## www.asics.ws ## info@... ## ## Author: Rudolf Usselmann ## rudi@... ## ################################################################################ FILES ################################################################################ opb2wb.edn 3- Rename the .edn to opb2wb.edn 4- Change PORT opb_rst to PORT rst in the .mpd file PORT opb_rst = OPB_Rst, DIR = IN, BUS = SOPB PORT rst = OPB_Rst, DIR = IN, BUS = SOPB 5- Make the rst signal visible in the EDK to check if it is connected to the right reset global signal of your design 6- Edit the edif file to change (program "Xilinx ngc2edif" (version "G.31a")) to (program "none") (As Rudi explains in one of his email, Xilinx documentation about generating exportable netlists is not very clear) 7- Select address 8000 0000 for the wrapper
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