FPGA для работы с 10G Ethernet Опции

[gin]

Всем добрый день! Может кто-нить поднимал на ПЛИС 10G Ethernet? Какие ПЛИС использовали для этого, и какие отладочные платы и каких производителей можете порекомендовать?
Заранее спасибо!

[novartis]

Это конечно логично, но вот при настройке в визарде этой корки при выборе rx_only сигнал pll_ref_clk не исчезает. К тому же в xcvr_user_guide.pdf есть такая картинка:



То есть реф клок все таки в приемной части у них задейстован ( в их реализации pcs)

[gin]

Это конечно логично, но вот при настройке в визарде этой корки при выборе rx_only сигнал pll_ref_clk не исчезает. К тому же в xcvr_user_guide.pdf есть такая картинка:



То есть реф клок все таки в приемной части у них задейстован ( в их реализации pcs)

Вот пытаюсь собрать в Quartus элементарную схему.
Прием 10G -> Передача 10G без всякой обработки.
Для приемника и передатчика использую корку 10GBASE-R PHY. Приемник имеет параметр rx_only, передатчик tx_only соответственно. Есть pll, который задает реф клок 322,265625 для передатчика. Но Quartus отказывается это собирать. Причем ругается именно на приемник.

Код

Error (14996): The Fitter failed to find a legal placement for all periphery components
    Error (14986): After placing as many components as possible, the following errors remain:
        Error (175001): Could not place HSSI PMA CDR REFCLK Select Mux, which is within 10GBASE-R PHY rx_10GBASE_R_PHY
            Info (14596): Information about the failing component:
                Info (175028): The HSSI PMA CDR REFCLK Select Mux name: rx_10GBASE_R_PHY:rx_10GBASE_R_PHY_inst|altera_xcvr_10gbaser:rx_10gbase_r_phy_ins
t|sv_xcvr_10gbaser_nr:xv_xcvr_10gbaser_nr_inst|sv_xcvr_10gbaser_native:ch[0].sv_x
cvr_10gbaser_native_inst|sv_xcvr_native:native_inst|sv_pma:inst_sv_pma|sv_rx_pma:
rx_pma.sv_rx_pma_inst|rx_pmas[0].rx_pma.cdr_refclk_mux0
            Info (14597): No legal location could be found for this component out of 54 considered location(s).  Reasons why each location could not be used are summarized below:
                Error (175006): Could not find path between source fractional PLL and the Receiver channel
                    Info (175026): Source: fractional PLL rx_10GBASE_R_PHY:rx_10GBASE_R_PHY_inst|altera_xcvr_10gbaser:rx_10gbase_r_phy_ins
t|sv_xcvr_10gbaser_nr:xv_xcvr_10gbaser_nr_inst|sv_xcvr_10gbaser_native:ch[0].sv_x
cvr_10gbaser_native_inst|g_fpll.altera_pll_156M~FRACTIONAL_PLL
                    Info (175021): The fractional PLL was placed in location FRACTIONALPLL_X0_Y55_N0
                    Error (175022): The Receiver channel could not be placed in any location to satisfy its connectivity requirements
                    Info (175029): 18 locations affected
                        Info (175029): Receiver channel containing PIN_AV2
                        Info (175029): Receiver channel containing PIN_AT2
                        Info (175029): Receiver channel containing PIN_AP2
                        Info (175029): Receiver channel containing PIN_AM2
                        Info (175029): Receiver channel containing PIN_AK2
                        Info (175029): Receiver channel containing PIN_AH2
                        Info (175029): Receiver channel containing PIN_AF2
                        Info (175029): Receiver channel containing PIN_AD2
                        Info (175029): Receiver channel containing PIN_AB2
                        Info (175029): Receiver channel containing PIN_Y2
                        Info (175029): Receiver channel containing PIN_V2
                        Info (175029): Receiver channel containing PIN_T2
                        Info (175029): and 6 more locations not displayed
                Error (175003): The I/O pad location is occupied (18 locations affected)
                    Info (175029): PIN_D39
                    Info (175029): PIN_F39
                    Info (175029): PIN_H39
                    Info (175029): PIN_K39
                    Info (175029): PIN_M39
                    Info (175029): PIN_P39
                    Info (175029): PIN_T39
                    Info (175029): PIN_V39
                    Info (175029): PIN_Y39
                    Info (175029): PIN_AB39
                    Info (175029): PIN_AD39
                    Info (175029): PIN_AF39
                    Info (175029): and 6 more locations not displayed
                Error (175007): Could not find uncongested path between source PLL output counter and the HSSI PMA CDR REFCLK Select Mux
                    Info (175026): Source: PLL output counter rx_10GBASE_R_PHY:rx_10GBASE_R_PHY_inst|altera_xcvr_10gbaser:rx_10gbase_r_phy_ins
t|sv_xcvr_10gbaser_nr:xv_xcvr_10gbaser_nr_inst|sv_xcvr_10gbaser_native:ch[0].sv_x
cvr_10gbaser_native_inst|g_fpll.altera_pll_156M~PLL_OUTPUT_COUNTER
                    Info (175021): The PLL output counter was placed in location PLLOUTPUTCOUNTER_X0_Y52_N1
                    Error (175022): The HSSI PMA CDR REFCLK Select Mux could not be placed in any location to satisfy its connectivity requirements
                    Info (175029): 18 locations affected
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y14_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y18_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y22_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y26_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y30_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y34_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y38_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y42_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y46_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y50_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y54_N39
                        Info (175029): HSSIPMACDRREFCLKSELECTMUX_X0_Y58_N39
                        Info (175029): and 6 more locations not displayed

И как я понимаю, основная проблема как раз этот самый реф клок для приемника

Сообщение отредактировал gin - Dec 16 2016, 09:30

Эскизы прикрепленных изображений