вышел хотфикс OrCAD/Allegro 17.2, HOTFIX VERSION: 008 Опции

[rom67]

Код

DATE: 10-29-2016   HOTFIX VERSION: 008
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CCRID   PRODUCT        PRODUCTLEVEL2   TITLE
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1644406 ALLEGRO_EDITOR SHAPE            Alternate symbol placement results in illegal parent identifier error
1647098 SIP_LAYOUT     OTHER            SiP crashes on symbol copy and rotate
1647154 APD            OTHER            Disconnected Clines not working
1648817 GRE            IFP_INTERACTIVE  Allegro PCB Editor stops responding on adding netgroups to a nested netgroup
1649829 CONCEPT_HDL    CORE             Project Manager: A delay is observed before the sub menus of the File and Tools menus appear
1652930 ALLEGRO_EDITOR OTHER            Command-line version of switchversion not working
1653109 ASDA           DESIGN_CORRUPTIO SDA not pulling latest library information for part
1655377 FLOWS          PROJMGR          Project Manager crashes on Windows 10

[rom67]

вышел хотфикс OrCAD/Allegro 17.2, HOTFIX VERSION: 027

Код

Fixed CCRs: SPB 17.2 HF027
09-29-2017
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CCRID   Product            ProductLevel2 Title
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1795353 ADW                FLOW_MGR      Tool unable to find project in windows_project.txt
1810386 ADW                FLOW_MGR      Error regarding not finding project in 'windows_project.txt'
1743732 ADW                LIBDISTRIBUTI adwserver -install does not give error if it cannot connect to server.
1804378 ALLEGRO_EDITOR     3D_CANVAS     Bend area issues in 3D Viewer
1795312 ALLEGRO_EDITOR     DATABASE      Cannot unlock symbols as status is changed to View on opening design
1803262 ALLEGRO_EDITOR     DATABASE      Donut pad With DYN_THERMAL_CON set to FULL_CONTACT has connectivity issues
1802183 ALLEGRO_EDITOR     DFM           Using mouse wheel to scroll error information in DRC Browser changes font size
1797222 ALLEGRO_EDITOR     DRC_CONSTR    Updating DRC results in error 'SPMHDB-403'
1792163 ALLEGRO_EDITOR     EDIT_ETCH     PCB Editor crashes on moving components
1806640 ALLEGRO_EDITOR     INTERFACES    Step Mapping not working in release 17.2-2016 Hotfix 025
1807278 ALLEGRO_EDITOR     INTERFACES    Running 'step_export_product_asm.exe' displays 'vcruntime140.dll' missing error
1807286 ALLEGRO_EDITOR     INTERFACES    The facet file (.xml) for the STEP model 'modelname.step' cannot be found.
1808006 ALLEGRO_EDITOR     INTERFACES    Facet file for step model cannot be found
1704335 ALLEGRO_EDITOR     MANUFACT      Documentation Editor shows an error about backdrill while no backdrill was used in the design
1800115 ALLEGRO_EDITOR     MANUFACT      IPC2581 Export giving error that backdrill is out of date even though no backdrill is defined in the design
1799444 ALLEGRO_EDITOR     PLACEMENT     Via Array - Boundary placement fails with error
1725242 ALLEGRO_EDITOR     SHAPE         'Same net shape to hole spacing' is only detecting the DRC and not voiding the shape
1804129 ALLEGRO_EDITOR     SHAPE         XHatch Shape not voiding properly
1805238 ALLEGRO_EDITOR     SHAPE         PCB Editor crashes while importing netlist
1803542 ALLEGRO_EDITOR     SKILL         Using axlPadstackEdit to change drill size causes via net to change in release 17.2-2016 Hotfix 025
1800774 APD                STREAM_IF     Only one pad in GDSII when running 'stream out' with the Flatten Geometry option
1804196 APD                STREAM_IF     Component is mirrored by X-axis instead of Y-axis on enabling mirror geometry
1803375 ASDA               IMPORT_BLOCK  Import HDL Block fails with message regarding Xnet states and DML independence
1807423 ASDA               NEW_PROJECT   SDA CPM file has erroneous date
1789400 CAPTURE            SCHEMATIC_EDI Capture schematic opens unannotated pages on search
1801573 CONCEPT_HDL        CONSTRAINT_MG Upreving release 16.6 design to 17.2-2016 adds NO_XNET_CONNECTION to some components
1810586 CONCEPT_HDL        CONSTRAINT_MG DE-HDL crashes when transferring XNET properties to similar components in a read-only block
1794169 CONCEPT_HDL        CORE          _automodel command crashes DE-HDL if PACK_IGNORE is set
1798672 CONCEPT_HDL        CORE          Dashes in design name creates an extra design folder in worklib after upreving to release 17.2-2016
1802258 CONCEPT_HDL        CORE          Locking unlocked components results in a warning (SPCOCN-3403)
1803019 CONCEPT_HDL        CORE          DE-HDL crashes on backannotation
1803615 CONCEPT_HDL        CORE          After running 'Mark for Variant', the block cannot be changed to blue
1804029 CONCEPT_HDL        CORE          Visibility issues when using the LOCK functionality
1806352 CONCEPT_HDL        CORE          Group Mirror is causing design corruption.
1806978 CONCEPT_HDL        CORE          Cannot mirror a group of  objects
1810387 CONCEPT_HDL        CORE          Mirroring groups causes erratic display and may corrupt database if project is saved
1812811 CONCEPT_HDL        CORE          Schematic group mirror not working
1810401 CONCEPT_HDL        INFRA         Add Signal Name: Cannot select suggested net name
1787409 CONCEPT_HDL        PDF           Minus character at the end of netname causes unexpected string concatenation during PDF Publish
1800931 CONSTRAINT_MGR     OTHER         Even after removing NO_XNET_CONNECTION on parallel termination, topology extracted has duplicate capacitors
1790106 CONSTRAINT_MGR     SCM           Cannot find the constraints file (0) in the schematic project
1787117 CONSTRAINT_MGR     UI_FORMS      Creating bundle in Constraint Manager crashes PCB Editor
1797384 ECW                METRICS       Pop-up metrics value tool tip is translucent, making values hard/impossible to read
1803226 ECW                METRICS       Pop-up metrics value tool tip is translucent, making values hard/impossible to read
1664059 ORBITIO            ALLEGRO_SIP_I Incorrect connectivity after .brd import
1799338 SIP_LAYOUT         DRC_CONSTRAIN Multi-threaded DRC fails with internal memory error even after setting shape_cache_size
1799499 SIP_LAYOUT         DRC_CONSTRAIN Multi-thread DRC fails
1806585 SIP_LAYOUT         DRC_CONSTRAIN Multi-threaded DRC update aborted: internal memory resource depleted
1809804 SIP_LAYOUT         DRC_CONSTRAIN Error message while updating DRCs in release 17.2-2016 Hotfix 026 regarding shape_cache_size
1788770 XTRACTIM           ENG           Translated bump / ball conductivity is wrong (PowerDC and XtractIM)