ARM startup code Опции

[doom13]

Приветствую.
Исходные данные:
1) LPC1766
2) ARM DS-5
3) CMSIS Packs Plug-in
4) GNU ARM OpenOCD
Проблема - при старте программы не происходит инициализация глобальных переменных. Как понимаю, надо добавить кусок кода (что-то типа __initialize_data и __initialize_bss) в startup.s + подправить scatter-file (пока используются стандартные для нового проекта)??? Аналогичный вопрос, но без ответа.

Код

; *************************************************************
; ** Scatter-Loading Description File generated by RTE CMSIS Plug-in **
; *************************************************************
LR_IROM1 0x00000000 0x40000 {  ; load region size_region
  ER_IROM1 0x00000000 0x40000 {; load address = execution address
   *.o (RESET, +First)
   *(InRoot$$Sections)
   .ANY (+RO)
  }
  RW_IRAM1 0x10000000 0x8000 {
   *.o (.bss)
  }
  RW_IRAM2 0x2007C000 0x8000 {
   .ANY (+RW +ZI)
  }
}

CODE

;/**************************************************************************//**
; * @file startup_LPC17xx.s
; * @brief CMSIS Cortex-M3 Core Device Startup File for
; * NXP LPC17xx Device Series
; * @version V1.10
; * @date 06. April 2011
; *
; * @note
; * Copyright © 2009-2011 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/

; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------

; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Stack_Size EQU 0x00002000

AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp


; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Heap_Size EQU 0x00002000

AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit


PRESERVE8
THUMB


; Vector Table Mapped to Address 0 at Reset

AREA RESET, DATA, READONLY
EXPORT __Vectors

__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler

; External Interrupts
DCD WDT_IRQHandler ; 16: Watchdog Timer
DCD TIMER0_IRQHandler ; 17: Timer0
DCD TIMER1_IRQHandler ; 18: Timer1
DCD TIMER2_IRQHandler ; 19: Timer2
DCD TIMER3_IRQHandler ; 20: Timer3
DCD UART0_IRQHandler ; 21: UART0
DCD UART1_IRQHandler ; 22: UART1
DCD UART2_IRQHandler ; 23: UART2
DCD UART3_IRQHandler ; 24: UART3
DCD PWM1_IRQHandler ; 25: PWM1
DCD I2C0_IRQHandler ; 26: I2C0
DCD I2C1_IRQHandler ; 27: I2C1
DCD I2C2_IRQHandler ; 28: I2C2
DCD SPI_IRQHandler ; 29: SPI
DCD SSP0_IRQHandler ; 30: SSP0
DCD SSP1_IRQHandler ; 31: SSP1
DCD PLL0_IRQHandler ; 32: PLL0 Lock (Main PLL)
DCD RTC_IRQHandler ; 33: Real Time Clock
DCD EINT0_IRQHandler ; 34: External Interrupt 0
DCD EINT1_IRQHandler ; 35: External Interrupt 1
DCD EINT2_IRQHandler ; 36: External Interrupt 2
DCD EINT3_IRQHandler ; 37: External Interrupt 3
DCD ADC_IRQHandler ; 38: A/D Converter
DCD BOD_IRQHandler ; 39: Brown-Out Detect
DCD USB_IRQHandler ; 40: USB
DCD CAN_IRQHandler ; 41: CAN
DCD DMA_IRQHandler ; 42: General Purpose DMA
DCD I2S_IRQHandler ; 43: I2S
DCD ENET_IRQHandler ; 44: Ethernet
DCD RIT_IRQHandler ; 45: Repetitive Interrupt Timer
DCD MCPWM_IRQHandler ; 46: Motor Control PWM
DCD QEI_IRQHandler ; 47: Quadrature Encoder Interface
DCD PLL1_IRQHandler ; 48: PLL1 Lock (USB PLL)
DCD USBActivity_IRQHandler ; 49: USB Activity interrupt to wakeup
DCD CANActivity_IRQHandler ; 50: CAN Activity interrupt to wakeup


IF :LNOT::DEF:NO_CRP
AREA |.ARM.__at_0x02FC|, CODE, READONLY
CRP_Key DCD 0xFFFFFFFF
ENDIF


AREA |.text|, CODE, READONLY

; Reset Handler

Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main

LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP


; Dummy Exception Handlers (infinite loops which can be modified)

NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP

Default_Handler PROC

EXPORT WDT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT I2C2_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT PLL0_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT EINT0_IRQHandler [WEAK]
EXPORT EINT1_IRQHandler [WEAK]
EXPORT EINT2_IRQHandler [WEAK]
EXPORT EINT3_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT BOD_IRQHandler [WEAK]
EXPORT USB_IRQHandler [WEAK]
EXPORT CAN_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT I2S_IRQHandler [WEAK]
EXPORT ENET_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
EXPORT PLL1_IRQHandler [WEAK]
EXPORT USBActivity_IRQHandler [WEAK]
EXPORT CANActivity_IRQHandler [WEAK]

WDT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
PWM1_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
I2C2_IRQHandler
SPI_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
PLL0_IRQHandler
RTC_IRQHandler
EINT0_IRQHandler
EINT1_IRQHandler
EINT2_IRQHandler
EINT3_IRQHandler
ADC_IRQHandler
BOD_IRQHandler
USB_IRQHandler
CAN_IRQHandler
DMA_IRQHandler
I2S_IRQHandler
ENET_IRQHandler
RIT_IRQHandler
MCPWM_IRQHandler
QEI_IRQHandler
PLL1_IRQHandler
USBActivity_IRQHandler
CANActivity_IRQHandler

B .

ENDP


ALIGN


; User Initial Stack & Heap

IF :DEF:__MICROLIB

EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit

ELSE

IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap

LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR

ALIGN

ENDIF


END

Спасибо.

[doom13]

Дофига что делает до main(), но толку мало,
последовательность выполняемых инструкций:

CODE

LDR R0, =__main
BX R0


__main:
000000cc: bl 0xd4 <__scatterload_rt2> ; unpredictable branch in IT block\n


__scatterload_rt2:
000000d4: add r0, pc, #40 ; (adr r0, 0x100 <__scatterload_null+30>)
000000d6: ldmia.w r0, {r10, r11}
000000da: add r10, r0
000000dc: add r11, r0
000000de: sub.w r7, r10, #1
000000e2: cmp r10, r11
000000e4: bne.n 0xea <__scatterload_rt2+22>

000000ea: subw lr, pc, #9
000000ee: ldmia.w r10!, {r0, r1, r2, r3}
000000f2: tst.w r3, #1
000000f6: it ne
000000f8: subne r3, r7, r3
000000fa: orr.w r3, r3, #1
000000fe: bx r3

__scatterload_copy:
00000108: subs r2, #16
0000010a: itt cs
0000010c: ldmiacs r0!, {r3, r4, r5, r6}
0000010e: stmiacs r1!, {r3, r4, r5, r6}
00000110: bhi.n 0x108 <__scatterload_copy>
00000112: lsls r2, r2, #29
00000114: itt cs
00000116: ldmiacs r0!, {r4, r5}
00000118: stmiacs r1!, {r4, r5}
0000011a: itt mi
0000011c: ldrmi r4, [r0, #0]
0000011e: strmi r4, [r1, #0]
00000120: bx lr

__scatterload_rt2:

000000e2: cmp r10, r11
000000e4: bne.n 0xea <__scatterload_rt2+22>
000000e6: bl 0x148 <__rt_entry_sh>
000000ea: subw lr, pc, #9
000000ee: ldmia.w r10!, {r0, r1, r2, r3}
000000f2: tst.w r3, #1
000000f6: it ne
000000f8: subne r3, r7, r3
000000fa: orr.w r3, r3, #1
000000fe: bx r3

__scatterload_zeroinit:
00000124: movs r3, #0
00000126: movs r4, #0
00000128: movs r5, #0
0000012a: movs r6, #0

0000012c: subs r2, #16 // ТУТ ДОЛГО КРУТИЛСЯ
0000012e: it cs //
00000130: stmia r1!, {r3, r4, r5, r6} //
00000132: bhi.n 0x12c <__scatterload_zeroinit+8> //

00000134: lsls r2, r2, #29
00000136: it cs
00000138: stmiacs r1!, {r4, r5}
0000013a: it mi
0000013c: strmi r3, [r1, #0]
0000013e: bx lr

__scatterload_rt2
000000e2: cmp r10, r11
000000e4: bne.n 0xea <__scatterload_rt2+22>
000000e6: bl 0x148 <__rt_entry_sh>

__rt_entry_sh:
00000148: bl 0x1762 <__user_setup_stackheap>

__user_setup_stackheap:
00001762: mov r5, lr
00001764: bl 0x17c0 <__user_libspace>

__user_libspace:
000017c0: ldr r0, [pc, #0] ; (0x17c4 <__user_libspace+4>)
000017c2: bx lr

__user_setup_stackheap:

00001768: mov lr, r5
0000176a: movs r5, r0
0000176c: mov r1, sp
0000176e: mov r3, r10
00001770: bic.w r0, r0, #7
00001774: mov sp, r0
00001776: add sp, #96 ; 0x60
00001778: push {r5, lr}
0000177a: bl 0x2a0 <__user_initial_stackheap>

__user_initial_stackheap:
000002a0: ldr r0, [pc, #16] ; (0x2b4 <__user_initial_stackheap+20>)
332 LDR R1, =(Stack_Mem + Stack_Size)
000002a2: ldr r1, [pc, #20] ; (0x2b8 <__user_initial_stackheap+24>)
333 LDR R2, = (Heap_Mem + Heap_Size)
000002a4: ldr r2, [pc, #20] ; (0x2bc <__user_initial_stackheap+28>)
334 LDR R3, = Stack_Mem
000002a6: ldr r3, [pc, #24] ; (0x2c0 <__user_initial_stackheap+32>)
335 BX LR
000002a8: bx lr

__user_setup_stackheap:

0000177e: ldmia.w sp!, {r5, lr}
00001782: mov.w r6, #0
00001786: mov.w r7, #0
0000178a: mov.w r8, #0
0000178e: mov.w r11, #0
00001792: bic.w r1, r1, #7
00001796: mov r12, r5
00001798: stmia.w r12!, {r6, r7, r8, r11}
0000179c: stmia.w r12!, {r6, r7, r8, r11}
000017a0: stmia.w r12!, {r6, r7, r8, r11}
000017a4: stmia.w r12!, {r6, r7, r8, r11}
000017a8: mov sp, r1
000017aa: bx lr

__rt_entry_sh:

0000014c: mov r1, r2

__rt_entry_postsh_1:
0000014e: bl 0x140 <__rt_lib_init>

__rt_lib_init:
00000140: push {r0, r1, r2, r3, r4, lr}

__rt_lib_init_user_alloc_1:
00000142: pop {r0, r1, r2, r3, r4, pc}

__rt_entry_postli_1:
00000152: bl 0x2c6 <main>

main:
000002c6: ldr r0, [pc, #36] ; (0x2ec)