Цитата(ViKo @ Dec 15 2017, 15:00)

wire keep_wire /* synthesis keep */;
Спасибо, добрый человек! У меня получилось:
Код
module temp_altera (
input clk_in,
output clk_out_delay
);
wire keep_wire_1 /* synthesis keep */;
assign keep_wire_1 = !clk_in;
wire keep_wire_2 /* synthesis keep */;
assign keep_wire_2 = !keep_wire_1;
wire keep_wire_3 /* synthesis keep */;
assign keep_wire_3 = !keep_wire_2;
assign clk_out_delay = keep_wire_3;
endmodule