https://www.alteraforum.com/forum/showthread.php?t=5860 взято.....
You can instance from VHDL a Verilog module and viceversa, each one in different files. This example shows how do it:
This is a VHDL entity called "White"
ENTITY white IS
PORT(
----------------------Inputs-------------------------------
clk : IN STD_LOGIC;
i_fval : IN STD_LOGIC;
i_media : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-------------------------------------------------------------
----------------------Outputs--------------------------------
o_enable : OUT STD_LOGIC;
o_exposure : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
-------------------------------------------------------------
);
END white;
This is a Verilog code that instances a white module called white0
white white0(
.clk(CCD_PIXCLK),
.i_fval(MEDIA_sfval[9:0]),
.i_media(MEDIA_sa[9:0]),
.o_enable(senable),
.o_exposure(sbalance)
);
Quartus II Web Edition does support mixed languages.
ModelSim-Altera Edition does NOT support mixed languages.Есть шанс, только надо поколдовать.....
https://www.fpgarelated.com/showthread/comp...pga/12748-1.php
MIX Verilog & VHDL, ткните носом
Mar 20 2018, 08:37
