Reconfigurable Computing Опции

[aosp]

Занимался ли кто–нибудь проблемой реконфигурируемых вычислений,
т.е. сменой аппараттного контекста в реальном времени применительно к решению задач управления/вычислений и т.д.
Хотелось бы пообсуждать.

[papasha]

Еще в тему. Пришел мне журнал X*Ce*lljo*urnal за лето 2004. Там есть ссылочка www.xilinx.com/xlnx/xweb/xil_tx_home.jsp . Там есть всякие статейки, в том числе Reconfiguring Block RAMs - программирование Block RAMs в процессе работы ПЛИС.

Там же ссылочка на XA*PP290 от 2003г (Two Flows for Partial Reconfiguration:
Module Based or Difference Based). Вот кратко:

An important feature in the Xilinx Virtex™ architecture is the ability to reconfigure a portion of the FPGA while the remainder of the design is still operational. Partial reconfiguration is useful for applications that require the loading of different designs into the same area of the device or the flexibility to change portions of a design without having to either reset or completely reconfigure the entire device. With this capability, entirely new application areas become possible:

• In-the-field hardware upgrades and updates to remote sites
• Runtime reconfiguration
• Adaptive hardware algorithms
• Continuous service applications
Other benefits include:
• Reduced device count
• Reduced power consumption
• More efficient use of available board space

This application note describes the exact steps required to successfully design, implement, verify, and actively reconfigure portions of Virtex/Virtex-E and Virtex-II/Virtex-II Pro™ series FPGAs. Two implementation flows are described in this application note: Module-based and Difference-based partial reconfiguration. References to Virtex or Virtex-E families also apply to Spartan™-II or Spartan-IIE families.
Note: Shutdown partial reconfiguration, where the non-reconfigurable portion is held in reset, is not within the scope of this application note.