Там два банка.
Код
void AT91F_InitSDRAM()
{
int i;
volatile int *pSDRAM = (int *)BASE_EBI_CS1_ADDRESS;
//* Configure PIOC as peripheral (D16/D31)
AT91F_SDRC_CfgPIO();
//* Setup MEMC to support CS1=SDRAM
AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A;
AT91C_BASE_EBI->EBI_CFGR = (AT91C_EBI_DBPUC & 0x00) | (AT91C_EBI_EBSEN & 0x00);
//* Init SDRAM
//* 1. A minimum pause of 200us is provided to precede any signal toggle
AT91C_BASE_SDRC->SDRC_CR = AT91C_SDRC_NC_8 | AT91C_SDRC_NR_12 | AT91C_SDRC_NB_2_BANKS | AT91C_SDRC_CAS_2
| 0x100 | 0x4000 | 0x8000
| 0x880000
| 0x21000000;
//* 2. A Precharge All command is issued to the SDRAM
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_PRCGALL_CMD;
*pSDRAM = 0;
//* 3. Eight Auto-refresh are provided
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_RFSH_CMD;
for(i=0;i<8;i++)
*pSDRAM = 0;
//* 4. A mode register cycle is issued to program the SDRAM parameters
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_LMR_CMD;
*(pSDRAM+0x80) = 0;
//* 5. Write refresh rate into SDRAMC refresh timer COUNT register
AT91C_BASE_SDRC->SDRC_TR = (AT91C_SDRC_COUNT & 0x2E0);
*pSDRAM = 0;
//* 6. A Normal Mode Command is provided, 3 clocks after tMRD is set
AT91C_BASE_SDRC->SDRC_MR = AT91C_SDRC_MODE_NORMAL_CMD;
*pSDRAM = 0;
}
вот с этим я эту плату с такими же микросхемами тестировал.