Импорт из PCAD в SPECCTRA получается, а наоборот - нет Опции

[=L.A.=]

Импорт из PCAD в SPECCTRA получается, а наоборот - нет

--------------------------------------------------------------------------------
# Parsing net section for net MDRV4.
# Parsing net section for net MDRV4E.
# Parsing net section for net MX1.
# Parsing net section for net MX2.
# Parsing net section for net MX3.
# Parsing net section for net MX4.
# Parsing net section for net RDY1.
# Parsing net section for net RDY2.
# Parsing net section for net VCC.
# Parsing test points section.
# Updating current design component placement and routes.
# Removing existing routes, test points, and their associated dimensions from current design.
# No component placement locations modified. No placement updates required.
# Error - Net D0 referenced in import file does not exist in current PCB design.
# SES file FAILED to import into current P-CAD PCB design!

[=L.A.=]

Заметил, что СПЕККТРА создает в корневом каталоге файл с примерно таким содержимым:


===============================================================================
# SPECCTRA ShapeBased Automation Software
# Copyright 1990-2000 Cadence Design Systems, Inc. All Rights Reserved.
# ===============================================================================
#
# Software licensed for sale by Cadence Design Systems, Inc.
# Current time = Sat Apr 07 22:24:38 2007
#
# SPECCTRA ShapeBased Automation Software V15.1 made 2003/11/17 at 23:03:32
# Running on: andro, OS Version: WindowsNT 5.1.2600, Architecture: Intel Pentium
# <<ERROR:>> Unrecognized argument: Files\SPECCTRA\BIN\sp.log
# Orphan shapes will not be removed.
# Licensing: The program will not obey any unlicensed rules
# SPECCTRA ShapeBased Automation Software will quit after -do file is executed!!
# Design Name .\03_PrdVitPar.DSN
# Batch File Name: 03_PrdVitPar.DO
# Output Log File Name: D:\Program
# Did File Name: .\04072224.did
# Current time = Sat Apr 07 22:24:42 2007
# PCB .
# Master Unit set up as: MM 100000
# PCB Limits xlo= 16.9500 ylo= 16.9500 xhi= 84.0500 yhi= 83.0500
# Total 1 Images Consolidated.
# Via 'CCTVIA_(Default)' z=1, 2 xlo= -0.5080 ylo= -0.5080 xhi= 0.5080 yhi= 0.5080
# Via bb1 z=1, 2 xlo= -0.5080 ylo= -0.5080 xhi= 0.5080 yhi= 0.5080
# Via V:CX40Y40D20A z=1, 2 xlo= -0.5080 ylo= -0.5080 xhi= 0.5080 yhi= 0.5080
# Via v:v50x22 z=1, 2 xlo= -0.6350 ylo= -0.6350 xhi= 0.6350 yhi= 0.6350
# Via via120d60 z=1, 2 xlo= -0.6000 ylo= -0.6000 xhi= 0.6000 yhi= 0.6000
#
# VIA Top Bottom
#
# Top ------------------ 'CCTVIA_(Default)'
# Bottom 'CCTVIA_(Default)' ------------------
#
# Wires Processed 0, Vias Processed 0
# Layers Processed: Signal Layers 2
# Components Placed 60, Images Processed 13, Padstacks Processed 21
# Nets Processed 29, Net Terminals 119
# PCB Area= 3660.000 EIC=9 Area/EIC=406.667 SMDs=32
# Total Pin Count: 129
# Signal Connections Created 90
#
# Design Rules --------------------------------------------
# Via Grid 0.0100 with offset 0.0000
# Layer Top Horz Signal Wire Grid 0.0100 with offset 0.0000, Width= 0.2540,

Clearance= 0.2500
# Layer Bottom Vert Signal Wire Grid 0.0100 with offset 0.0000, Width= 0.2540,

Clearance= 0.2500
# Cpu Time = 0:00:00 Elapsed Time = 0:00:00