Сравнение чисел (больше/меньше), Наибыстрый алгоритм Опции

[Serega Doc]

Как написать быстрое сравнение безннаковых чисел на больше меньше?

[des00]

2 des00

А как вы получите знак не выполнив вычитания?
Или
diff<={1'b0, data0}-{1'b0,data1};
-это не 49 битные операнды?

Вот этот код

module proj
(
input sys_clk,
input [47:0] data0,
input [47:0] data1,
output sing
);

wire [47:0] data0, data1;
wire sing;

reg [48:0] d;

assign sing = d[48];

always @(posedge sys_clk)
begin
d <= {1'b0,data0} - {1'b0,data1};
end

endmodule

Вот отчеты синтезатора
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
; Fitter Status ; Successful - Wed Apr 13 17:49:41 2005 ;
; Quartus II Version ; 4.2 Build 178 01/19/2005 SP 1 SJ Full Version ;
; Revision Name ; Bosik ;
; Top-level Entity Name ; Bosik ;
; Family ; Cyclone ;
; Device ; EP1C6F256C8 ;
; Timing Models ; Final ;
; Total logic elements ; 49 / 5,980 ( < 1 % ) ;
; Total pins ; 98 / 185 ( 52 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 92,160 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-----------------------+-----------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-------------------+-------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------------------+-------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 8.629 ns ; B[19] ; Compar:inst|d[48] ; ; Clock ; 0 ;
; Worst-case tco ; N/A ; None ; 8.353 ns ; Compar:inst|d[48] ; AGB ; Clock ; ; 0 ;
; Worst-case th ; N/A ; None ; -1.691 ns ; A[39] ; Compar:inst|d[48] ; ; Clock ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-------------------+-------------------+------------+----------+--------------+

При запросе максимальной тактовой в 475 метров
квартус ругнулся
Clock Setup: 'Clock' N/A 475.06 MHz ( period = 2.105 ns ) Restricted to 275.03 MHz ( period = 3.636 ns ) Compar:inst|d[48] AGB Clock Cloc

вот еще оттуда

Info: Clock "Clock" Internal fmax is restricted to 275.03 MHz between source register "Compar:inst|d[48]" and destination register "AGB"
Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 1.049 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y14_N9; Fanout = 1; REG Node = 'Compar:inst|d[48]'
Info: 2: + IC(0.740 ns) + CELL(0.309 ns) = 1.049 ns; Loc. = LC_X32_Y14_N0; Fanout = 0; REG Node = 'AGB'
Info: Total cell delay = 0.309 ns ( 29.46 % )
Info: Total interconnect delay = 0.740 ns ( 70.54 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "Clock" to destination register is 2.962 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 2; CLK Node = 'Clock'
Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X32_Y14_N0; Fanout = 0; REG Node = 'AGB'
Info: Total cell delay = 2.180 ns ( 73.60 % )
Info: Total interconnect delay = 0.782 ns ( 26.40 % )
Info: - Longest clock path from clock "Clock" to source register is 2.962 ns
Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 2; CLK Node = 'Clock'
Info: 2: + IC(0.782 ns) + CELL(0.711 ns) = 2.962 ns; Loc. = LC_X33_Y14_N9; Fanout = 1; REG Node = 'Compar:inst|d[48]'
Info: Total cell delay = 2.180 ns ( 73.60 % )
Info: Total interconnect delay = 0.782 ns ( 26.40 % )
Info: + Micro clock to output delay of source is 0.224 ns
Info: + Micro setup delay of destination is 0.037 ns