ibuf в ISE Опции

[DLR]

Необходимо подключить несколько входных буферов к шине,
Написал такой текст:
COMPONENT ibuf PORT ( I : IN STD_LOGIC;
O : OUT STD_LOGIC );

U0 : ibuf PORT MAP(
I => Ii(0),
O => Io(0) );

U1 : ibuf PORT MAP(
I => Ii(1),
O => Io(1) );
*
*
*
но при трассировке в ModelSim 6.0c, при подаче сигнала на шину Ii на шине Io одни "UUUU...".
Почему так происходит?

То же самое и с IObuf...

[DLR]

Вот они!
Приложить не получилось, так что вставил!

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity B_LV is
Port ( DI : in std_logic;
DO : out std_logic;
CLK : in std_logic;
Dp : inout std_logic;
Dm : inout std_logic;
T : in std_logic);
end B_LV;

architecture Behavioral of B_LV is

-- COMPONENT IOBUF_LVDS
COMPONENT IOBUF_LVDS
PORT ( I : IN STD_LOGIC;
O : OUT STD_LOGIC;
IO : INOUT STD_LOGIC;
T : IN STD_LOGIC );

END COMPONENT;

COMPONENT FD
PORT ( D : IN STD_LOGIC;
Q : OUT STD_LOGIC;
C : IN STD_LOGIC );
END COMPONENT;

SIGNAL Dvo : std_logic;
SIGNAL Dvi : std_logic;
SIGNAL Dinv : std_logic;
SIGNAL Dvrem : std_logic;

attribute iob : string;
attribute OPEN_DRAIN : string;
attribute FAST : string;
attribute IOB of FD : component is "TRUE";
attribute OPEN_DRAIN of Dp : signal is "TRUE";
attribute OPEN_DRAIN of Dm : signal is "TRUE";
attribute FAST of Dp : signal is "true";

begin
-- ATTRIBUTE IOB <= true;



D0 : fd PORT MAP (
D => DI,
Q => Dvo,
C => CLK );

D1 : fd PORT MAP (
D => Dvi,
Q => DO,
C => CLK );

Dinv <= not(Dvo);

IO0 : IOBUF_LVDS PORT MAP(
I => Dvo,
O => Dvi,
T => T,
IO =>Dp );

IO1 : IOBUF_LVDS PORT MAP(
I => Dinv,
O => Dvrem,
T => T,
IO =>Dm );

end Behavioral;

[andrew_b]

Компоненты IOBUF_LVDS и FD --- примитивы Xilinx. Нужны их симуляционные модели. Делается так:

Код

-- syntesis translate_off
library UNISIM;
use UNISIM.VComponents.all;
-- syntesis translate_on

architecture Behavioral of B_LV is

COMPONENT IOBUF_LVDS
PORT(
        I   : IN STD_LOGIC;
        O  : OUT  STD_LOGIC;
        IO : INOUT STD_LOGIC;
        T   : IN STD_LOGIC
       );
END COMPONENT;

COMPONENT FD
PORT(
        D : IN STD_LOGIC;
        Q : OUT  STD_LOGIC;
        C  : IN STD_LOGIC
      );
END COMPONENT;

-- syntesis translate_off
-- sumulation models
for all: IOBUF_LVDS use
    entity UNISIM.IOBUF_LVDS(IOBUF_LVDS_V);

for all: FD use
    entity UNISIM.FD(FD_V);
-- syntesis translate_on