SCAN-CHAINS Опции

[-=Vitaly=-]

Здравствуйте!

Хочу сгенерировать скан-цепочки типа multiplexed_flip_flip в DC.
Есть 2 вопросика.

1. У меня в дизайне есть клок CLK, он же будет использоваться для скан-цепочки.
это опция -clock_mixing no_mux?

2. На что влияет опция -methodology например full_scan?

Спасибо!

[grigorik]

Здравствуйте!

Хочу сгенерировать скан-цепочки типа multiplexed_flip_flip в DC.
Есть 2 вопросика.

1. У меня в дизайне есть клок CLK, он же будет использоваться для скан-цепочки.
это опция -clock_mixing no_mux?

2. На что влияет опция -methodology например full_scan?

Спасибо!

1. У меня в дизайне есть клок CLK, он же будет использоваться для скан-цепочки.
это опция -clock_mixing no_mux?

-clock_mixing don't have option "no_mux" the right is no_mix.
no_mix is the default: and it means that all cells must be clocked by the same edge of the same clock. You have one clock if all triggers are working with the same egdes you have no problem.
Otherwies if you want both types of triggers (rise edge and fall edge) to be included in scan chain use "-clock_mixing mix_edges".

2. На что влияет опция -methodology например full_scan?
This is from user guide:

In the full-scan methodology, DFT Compiler replaces all sequential cells in your design with their scannable equivalents during scan insertion.

If a sequential cell cannot be made scannable because of test design rule violations or because you have explicitly excluded the cell from the scan chain, DFT Compiler classifies the cell as a black box sequential cell during test design rule checking. Black box sequential cells lower fault coverage results. See “Scan Design Techniques” for more information on sequential cell classifications.

Because it is a more predictable methodology, full scan typically provides higher fault coverage in a shorter period of time than partial scan. Full scan also provides improved diagnostic capabilities compared to partial scan.

Because full scan substitutes scannable equivalents for all sequential cells, however, it increases design area and decreases design performance. Integration with synthesis minimizes the area and performance impact of full scan. In most cases, performance can be maintained in a full-scan design, but at the cost of additional area.

Maybe it will help you.