synplify + ise не размещают oe_триггер в iob- как победить? Опции

[gosha]

synplify 9.6 используется для синтеза.
ise 10 implementation.
virtex 2 pro.
В схеме iob 2 триггера присутствуют: для oe и data.

ise триггер sdram_dq_out размещает в iob.
ise триггер sdram_dq_en не размещает в iob - как победить?

Спасибо.

Код

module top ( ....
inout  [63:0] sdram_dq;
    
wire [63:0] sdram_dq, sdram_dq_o, sdram_dq_oe;

bufif0 sdram_dq_buf [63:0] (sdram_dq, sdram_dq_o, sdram_dq_oe);

memory_hub memory_hub_insertion (.sdram_dq_i(sdram_dq),.sdram_dq_o(sdram_dq_o),.sdram_dq_oe(sdram_dq_oe));

.....

Код

entity memory_hub is  port(
         sdram_dq_i :  in std_logic_vector(63 downto 0);
         sdram_dq_o : out std_logic_vector(63 downto 0);
         sdram_dq_oe: out std_logic_vector(63 downto 0);
signal sdram_dq_out :    std_logic_vector(63 downto 0);
signal sdram_dq_en : std_logic_vector(63 downto 0);
attribute syn_keep of sdram_dq_en : signal is true;
attribute syn_keep of precharge_enable : signal is true;
attribute xc_props of sdram_dq_en  : signal is "IOB=TRUE";
attribute xc_props of sdram_dq_out : signal is "IOB=TRUE";
    .................................
sdram_dq_o  <= sdram_dq_out;
sdram_dq_oe <= sdram_dq_en;
process (wb_clk)
begin
    if (wb_clk'event and wb_clk = '1') then
        if cmd_write then
            sdram_dq_out <= sdram_di;
            precharge_enable <= false;
            sdram_dq_en <= (others => '0');
        else
            sdram_dq_out <= sdram_dq_out;
            sdram_dq_en <= (others => '1');
            precharge_enable <= true;
        end if;
    end if;
end process;

Код

  Maximum Data Path: memory_hub_insertion/precharge_enable to sdram_dq[55]
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y21.YQ      Tcko                  0.419   sdram_dq_oe[0]
                                                       memory_hub_insertion/precharge_enable
    J29.T1               net (fanout=68)       6.397   sdram_dq_oe[0]
    J29.PAD              Tiotp                 3.031   sdram_dq[55]
                                                       sdram_dq_iobuf[55]/OBUFT
                                                       sdram_dq[55]
    -------------------------------------------------  ---------------------------
    Total                                      9.847ns (3.450ns logic, 6.397ns route)
                                                       (35.0% logic, 65.0% route)

--------------------------------------------------------------------------------
Slack:                  8.047ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               memory_hub_insertion/precharge_enable (FF)
  Destination:          sdram_dq[53] (PAD)
  Source Clock:         PLL_XC_H_c rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      9.577ns (Levels of Logic = 1)
  Clock Path Delay:     2.376ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

Прикрепленные файлы

 iob.pdf ( 19.85 килобайт ) Кол-во скачиваний: 106

 

[Bar]

Попробуйте директиву syn_useioff

Из хелпа synplify:
entity test is
port (d : in std_logic_vector (3 downto 0);
clk : in std_logic;
q : out std_logc_vector (3 downto 0);
attribute syn_useioff : boolean;
attribute syn_useioff of q : signal is true;
end test;

У меня помогло, правда я на верилоге делал.