Так можно
Код
reg [7:0] old0;
reg [7:0] old1;
reg [7:0] old2;
reg [7:0] old3;
input [7:0] dataIn;
input [7:0] cmpw0;
input [7:0] cmpw1;
input [7:0] cmpw2;
input [7:0] cmpw3;
output ok;
always @ (posedge clk)
begin
old0 <= dataIn;
old1 <= old0;
old2 <= old1;
old3 <= old2;
end
assign ok = ((old0 == cmpw0) && (old1 == cmpw1) && (old2 == cmpw2) && (old3 == cmpw3) );
/* не собирал, на ошибки не проверял, дома нет софта */
Сообщение отредактировал Methane - Mar 15 2009, 12:18