|
Залил upload/doc/at91sam9262.pdf
Чип приличный, трудно придумать - чего в нем нет
Однако BGA 0.5 мм, но 4 ряда
Features
•Incorporates the ARM926EJ-S™ ARM® Thumb® Processor
–DSP Instruction Extensions, ARM Jazelle® Technology for Java™ Acceleration
–16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer
–200MIPS at 180MHz
–Memory Management Unit
–EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support
–Mid-level Implementation Embedded Trace Macrocell™
•Additional Embedded Memories
–One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed
–One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Matrix Speed
–Two 8 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed
•Dual External Bus Interface (EBI0 and EBI1)
–EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash/SmartMedia™ and CompactFlash™
–EBI1 Supports SDRAM Static Memory and ECC Enabled NAND Flash SmartMedia
•GPS Engine
–14-channel, High Sensitivity, High Accuracy, Fast Acquisition
–WAAS Enabled, DGPS, RTCM104 Enabled, NMEA Data Format
•LCD Controller
–Supports Passive or Active Displays
–Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in TFT Mode
–Up to 16M Colors in TFT Mode, Resolution up to 2048x2048, Supports Wider Screen Buffers
•2D Graphics Accelerator
–Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing
•Image Sensor Interface
–ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate
–12-bit Data Interface for Support of High Sensibility Sensors
–SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format
•USB 2.0 Full Speed (12 Mbits per second) Host Double Port
–Dual On-chip Transceivers
–Integrated FIFOs and Dedicated DMA Channels
•USB 2.0 Full Speed (12 Mbits per second) Device Port
–On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs
•USB OTG
–Complies with the On-the-Go Supplement to the USB 2.0 Specification, Revision 1.0
–Complies with the OTG Transceiver Interface Specification, Revision 0.75a
•Ethernet MAC 10/100 Base T
–Media Independent Interface or Reduced Media Independent Interface
–28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit
•Bus Matrix
–Nine 32-bit-layer Matrix, Allowing a Total of 28.8Gbps of On-chip Bus Bandwidth
–Boot Mode Select Option, Remap Command
•Fully-featured System Controller, including
–Reset Controller, Shut Down Controller
–Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes
–Clock Generator and Power Management Controller
–Advanced Interrupt Controller and Debug Unit
–Periodic Interval Timer, Watchdog Timer and Double Real-Time Timer
•Reset Controller (RSTC)
–Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control
•Shut Down Controller (SHDC)
–Programmable Shutdown Pin Control and Wake-up Circuitry
•Clock Generator (CKGR)
–32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock
–3 to 20 MHz On-chip Oscillator and Two up to 240 MHz PLLs
•Power Management Controller (PMC)
–Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
–Four Programmable External Clock Signals
•Advanced Interrupt Controller (AIC)
–Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
–Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
•Debug Unit (DBGU)
–2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
•Periodic Interval Timer (PIT)
–20-bit interval Timer plus 12-bit interval Counter
•Watchdog Timer (WDT)
–Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
•Two Real-Time Timer (RTT)
–32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
•Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD and PIOE)
–160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os
–Input Change Interrupt Capability on Each I/O Line
–Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
•Twenty Peripheral DMA Controller Channels (PDC)
•One Advanced Encryption System (AES)
–128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
–Buffer Encryption/decryption Capabilities with PDC
•One Part 2.0A and Part 2.0B Compliant CAN Controller
–16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter
•Two Multimedia Card Interface (MCI)
–SDCard/SDIO and MultiMedia Card Compliant
–Automatic Protocol Control and Fast Automatic Data Transfers with PDC
–Two SDCard Slots for Each Controller
•Two Synchronous Serial Controllers (SSC)
–Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
–I²S Analog Interface Support, Time Division Multiplex Support
–High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
•One AC97 Controller (AC97C)
–6-channel Single AC97 Analog Front-end Interface, Slot Assigner
•Three Universal Synchronous/Asynchronous Receiver Transmitters (USART)
–Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation, Manchester Encoding/Decoding
–Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
•Two Master/Slave Serial Peripheral Interface (SPI)
–8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
–Synchronous Communications at up to 90Mbits/sec
•One Three-channel 16-bit Timer/Counters (TC)
–Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
–Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
•One Four-channel 16-bit PWM Controller (PWMC)
•One Two-wire Interface (TWI)
–Master Mode Support, All Two-wire Atmel EEPROM’s Supported
•IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
•Required Power Supplies:
–1.08V to 1.32V for VDDCORE and VDDBU
–3.0V to 3.6V for VDDOSC, VDDPLL and VDDIOP0 (Peripheral I/Os)
–1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) and for VDDIOM0/VDDIOM1 (Memory I/Os)
•Available in a 320-ball LFBGA Package
|
AT91SAM9262 (новый, еще не объявленный чип), Промелькнула документация на AT91SAM9262
Nov 21 2005, 18:06
К примеру, я интересовался, будут ли ревизии AT91RM9200 с исправлениями - ответ отрицательный.
