SPice & UCXXX, модель? Опции

[vlvl@ukr.net]

Народ, подскажите где можно найти SPice модели на PWM UCXXX.
В частности на UCХ84Х? Очень хочется побаловаться
На сайте Тексуса не нашел.

[jackBU]

Я оставил вывод Rt/Ct свободным. Частота и "мертвое время" задаются внутри модели с помощью параметров DEADTIME и PERIOD.

*** SG1844 ***


* The following model for the 1844 was obtained by consulting the data sheets
* and corresponding with Silicon General. A number of simplifications were
* made to speed up the model, among these we have:
* (a) replaced the oscillator with ideal voltage sources
* ( simplified the output stage (only two bipolars per output driver),
* © used digital simulation for the internal logic.
* (d) if u want to check for feedback loading use ea184s1

* The impact of that these simplifications must be considered in the context
* of the parameters of the circuit, and the circuit being examined. The
* above list might change as we get feedback.

.subckt sg1844
+ 1 ; compensation
+ 2 ; - error amp (fb)
+ 3 ; I sense
+ 5 ; ground
+ 6 ; output
+ 7 ; vcc
+ 8 ; vref
+ params:
+ period = 22.5u ; internal clock period
+ deadtime = 2e-6 ; internal clock deadtime

* Pin 4 was not included (Rt Ct) due to (a) above

xdigpwr 5 DPWR DGND DIGIFPWR

eref ref DGND value={5*v(uvcompaa)}
G7 7 DGND VALUE={11M*V(UVCOMPAA)}
rref ref 0 1g
v8a 8a 8 0
r8 8 0 1g
r8a 8a 0 1g
eref1 8a DGND value={v(ref)-v(8b)}
xll1 8a loadrc
xload3 3 loadrc
xll2 8b loadrc
edeg 8b 0 table={i(v8a)} (0 0) (50m 25m) (80m 1) (100m 4)
o6 7 DGND uvcomp dgtlnet=uvlo io_std
.model uvcomp doutput(
+ s0name=0 s0vlo= 10 s0vhi=100
+ s1name=1 s1vlo= -30 s1vhi=16)
v2p5 intref DGND 2.5
x1 intref 2 1 DPWR DGND ea184s
escaledown eao DGND table={(v(1,DGND)-1.4)*.333} (0 0) (1,1)
reao eao eaoa 1k
ceao eaoa 0 10p
o7 3 eao compmod dgtlnet=reset io_std
.model compmod doutput(
+ s0name=0 s0vlo= -300 s0vhi=0
+ s1name=1 s1vlo= 0 s1vhi=300)
v_clkset ramp DGND pulse(1 3 .1ns
+ {period-deadtime-2*deadtime/100} {deadtime} {deadtime/100} {period} )
x15 ramp set DPWR DGND gen_clk
ustart stim(1,1) DPWR DGND 87 io_stm
+ 0s 0
+ 20ns 1 ; q and clk fed into or
uhi stim(1,1) DPWR DGND 222 io_stm 0s 1
usrdps srff(1) DPWR DGND 87 222 222 setz reset q qb d0_gff io_std
udl1 dlyline DPWR DGND set setz dlmod io_std
udl3 dlyline DPWR DGND qb qbd dlmod1 io_std
.model dlmod udly(dlyty=5n)
.model dlmod1 udly(dlyty=150n)
u10 dff(1) DPWR DGND 222,87,setz,21 20 21 d0_eff io_std
x119 20 set uvlo qbd 7 6 DPWR DGND outst445
v1 one 0 1
x78 uvlo uvcompaa one 0 DtoAcone
vp7 p7 DGND .7
rp7 p7 DGND 1g
serr 1 p7 uvcompaa 0 sofferr
sout 6 DGND uvcompaa 0 soffmod
.model sofferr vswitch (ron=50 roff=100meg von=.1 voff=.9)
.model soffmod vswitch (ron=100 roff=100meg von=.1 voff=.9)
.ends sg1844


Виноват, не смог прикрепить файл. . Могу выслать по почте.

[vlvl@ukr.net]

Спасибо всем, все получилось. Я тормознул с описанием схемы