ST ARM STR710x; CrossWorks, кто что скажет? Опции

[Evgeny_CD]

Посмотрел я на STR710 - хорошая штуковина!

* 256K FLASH, 64K RAM
* набор периферии внушительный - один HDLC чего стоит!
* внешняя шина - хоть и не быстрая и 16 битная, но зато какой-нибудь
АCEX 1K за 9$ поставил - и твори нестандартную периферию.
* цена
* доcтупность здесь на складах
* дешевые (относительно) поделочные платы за 65$.
* заявлена поддержка CrossWorks

К процу ОЧЕНЬ нехилая библиотека софта в исходниках прилагается.

Сама либа
http://www.st.com/stonline/products/suppor...tr71xlibstd.zip

Мануал
http://www.st.com/stonline/products/literature/um/10780.pdf

Вопросы.

* что насчет глючности и несоответствия доке:
- ремапер памяти
- контроллер прерываний - он там прерывания не пропускает?
- UART
- I2C
- SPI
- таймера
- HDLC

* реальная скорость на 50 Мгц при выполнении из FLASH
- ARM mode
- THUMB mode

* сколь хорошо камень поддержан CrossWorks (например, по сравнению с LPCxxx)?

* общие впечатления от камня?

Заранее спасибо всем ответившим.

[yosephcz]

Izvinite, ja budu pisat' po English, segodn'ja u menja net russkoj klaviatury:



First - Startup.s from CW:

.section .vectors, "ax"
.code 32
.align 0

/*****************************************************************************
* Exception Vectors *
*****************************************************************************/
_vectors:
ldr pc, [pc, #reset_handler_address - . - 8] /* reset */
ldr pc, [pc, #undef_handler_address - . - 8] /* undefined instruction */
ldr pc, [pc, #swi_handler_address - . - 8] /* swi handler */
ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
nop

ldr pc, [pc, #-0x0808] //by yosephcz - EIC_IVR register
////ldr pc, [pc, #irq_handler_address - . - 8] /* irq */

ldr pc, [pc, #fiq_handler_address - . - 8] /* fiq */
...





Second - you must properly configure EIC - for example:

#define SIR(n) (*(&EIC_SIR0 + n))
...
EIC_IVR = 0x40000000;
...
SIR(ivector_) = priority_ | ((UINT32)pISRfce_ << 16);
...
enable IRQ etc.
....


Where:
A/ "((UINT32)pISRfunction_ << 16)" is lower 16bits of address of your ISR routine. "pISRfunction_" is pointer to your ISR routine. This 16bits will be filled in lower 16bits of EIC_IVR register when IRQ appears. Higher 16bits of EIC_IVR register is filled in my CPU init code "EIC_IVR = 0x40000000;".
B/ priority_ is IRQ priority


ACTION:
When IRQ appears, EIC_IVR is filled with address of your ISR routine and CPU jumps to the address which is filled in EIC_IVR register. EIC_IVR is filled automatically by CPU according to the active interrupt source. For more please see STR71x user manual - EIC (Enhanced Interrupt Controller).

Note: make sure that 0x40000000 is correct offset of your ISR routine. I have for example created flash memory section from 0x40002000, where my ISR routines are linked. I have theoretically 0xE000 Bytes for ISR code.


I think that this situation is much better on Philips LPC2xxx devices, where you can fill 32bit address of your ISR routine. On STR71x you can fill only 16bits and higher 16bits you must fill for ALL ISR functions to the EIC_IVR register = your ISR functions must be linked in 0xFFFF Bytes memory block (it means max. 64kB "only").


This mechanism is the fastest solution of IRQ handling. This mechanism is very similar to the LPC2xxx. Or you can do the other method whis is written in ST examples, but this mechanism is slower.



YOSEPHCZ