помогите перевести в код IAR Опции

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Привет всем!

Помогите пожалуйста отконфигурить at91sam7se32 на работу с внешней флешкой 29 серии. Нужно отремапить ее на адрес 0x10000000.
Т.е. стандартный пример кода, который стартует из внутренней флешки проца, ремапит внешнююю флеш на адрес 0x10000000 и передает управление на этот адрес. Благодарность моя не будет иметь границ

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Код был взят отсюда http://www.embedded-os.de/source/SAM7SExx_...ter_MemInit.zip


Помогите скомпилировать данный код в IAR или подскажите под какую среду он заточен.
Это пример инициализации флеш и озу для процессора AT91SAM7SE

Код

void SAM7SE_MemInit(void)
{
  
    /********************************************************
    *            init the external SMC A/D bus              *
    ********************************************************/
                                                           // Configure PIO controllers to periph mode
    AT91S_PIOB_BSR  = (AT91S_PB00_A0_NBS0 | AT91S_PB01_A1_NBS2 | AT91S_PB02_A2  | AT91S_PB03_A3  | AT91S_PB04_A4  | AT91S_PB05_A5  | AT91S_PB06_A6  | AT91S_PB07_A7  |
                       AT91S_PB08_A8      | AT91S_PB09_A9      | AT91S_PB10_A10 | AT91S_PB11_A11 | AT91S_PB12_A12 | AT91S_PB13_A13 | AT91S_PB14_A14 | AT91S_PB15_A15 |
                       AT91S_PB16_A16_BA0 | AT91S_PB17_A17_BA1 );
    AT91S_PIOB_PDR  = (AT91S_PB00_A0_NBS0 | AT91S_PB01_A1_NBS2 | AT91S_PB02_A2  | AT91S_PB03_A3  | AT91S_PB04_A4  | AT91S_PB05_A5  | AT91S_PB06_A6  | AT91S_PB07_A7  |
                       AT91S_PB08_A8      | AT91S_PB09_A9      | AT91S_PB10_A10 | AT91S_PB11_A11 | AT91S_PB12_A12 | AT91S_PB13_A13 | AT91S_PB14_A14 | AT91S_PB15_A15 |
                       AT91S_PB16_A16_BA0 | AT91S_PB17_A17_BA1 );
    AT91S_PIOC_ASR  = (AT91S_PC00_D0 | AT91S_PC01_D1 | AT91S_PC02_D2  | AT91S_PC03_D3  | AT91S_PC04_D4  | AT91S_PC05_D5  | AT91S_PC06_D6  | AT91S_PC07_D7  |
                       AT91S_PC08_D8 | AT91S_PC09_D9 | AT91S_PC10_D10 | AT91S_PC11_D11 | AT91S_PC12_D12 | AT91S_PC13_D13 | AT91S_PC14_D14 | AT91S_PC15_D15 |
                       AT91S_PC16_A18_NWAIT);
    AT91S_PIOC_BSR  = (AT91S_PC21_NWR0_NWE | AT91S_PC22_NRD);
    AT91S_PIOC_PDR  = (AT91S_PC00_D0 | AT91S_PC01_D1 | AT91S_PC02_D2  | AT91S_PC03_D3  | AT91S_PC04_D4  | AT91S_PC05_D5  | AT91S_PC06_D6  | AT91S_PC07_D7  |
                       AT91S_PC08_D8 | AT91S_PC09_D9 | AT91S_PC10_D10 | AT91S_PC11_D11 | AT91S_PC12_D12 | AT91S_PC13_D13 | AT91S_PC14_D14 | AT91S_PC15_D15 |
                       AT91S_PC16_A18_NWAIT | AT91S_PC21_NWR0_NWE | AT91S_PC22_NRD);
    /********************************************************
    *            init the NOR  interface on NCS0            *
    *                    ( AT49BV040B )                     *
    *  start:   0x 1000 0000       size:   0x 0008 0000     *
    ********************************************************/
    AT91S_PIOC_BSR  = AT91S_PC23_NCS0;                     // NCS0 config
    AT91S_PIOC_PDR  = AT91S_PC23_NCS0;
    AT91S_SMC_CSR->s[0] =                                  // Configure SMC Register
                      AT91S_SMC_CSR_NWS_2            |     // 1 wait states required by the NOR Flash device
                      AT91S_SMC_CSR_WSEN_EN          |     // NWS register enabled
                      AT91S_SMC_CSR_TDF_0            |     // 0 Data Float Time Cycles required by the NOR Flash device
                      AT91S_SMC_CSR_BAT_8BIT         |     // (one) 8-bit device connected over the bus
                      AT91S_SMC_CSR_DBW_8            |     // 8-bit Data Bus Width
                      AT91S_SMC_CSR_DRP_STD          |     // Standard Read protocol required by the NOR Flash device
                      AT91S_SMC_CSR_ACSS_STD         |     // Standard address to chip select
                      AT91S_SMC_CSR_RWSETUP_0        |     // 0 Read/Write Setup time required by the NOR Flash device
                      AT91S_SMC_CSR_RWHOLD_0        ;     // 0 Read/Write Hold time required by the NOR Flash device
    /********************************************************
    *            init the sRAM interface on NCS2            *
    *                   ( K6X4008T1F-70 )                   *
    *  start:   0x 3000 0000       size:   0x 0008 0000     *
    ********************************************************/
    AT91S_PIOA_BSR  = AT91S_PA20_NCS2;                     // NCS2 config
    AT91S_PIOA_PDR  = AT91S_PA20_NCS2;
    AT91S_SMC_CSR->s[2] =                                  // Configure SMC Register
                      AT91S_SMC_CSR_NWS_4            |     // 4 wait states required by the sRAM device
                      AT91S_SMC_CSR_WSEN_EN          |     // NWS register enabled
                      AT91S_SMC_CSR_TDF_1            |     // 1 Data Float Time Cycles required by the sRAM device
                      AT91S_SMC_CSR_BAT_8BIT         |     // (one) 8-bit device connected over the bus
                      AT91S_SMC_CSR_DBW_8            |     // 8-bit Data Bus Width
                      AT91S_SMC_CSR_DRP_STD          |     // Standard Read protocol required by the sRAM device
                      AT91S_SMC_CSR_ACSS_0           |     // 1 cycle address to chip select at begin and end
                      AT91S_SMC_CSR_RWSETUP_0        |     // 0 Read/Write Setup time required by the sRAM device
                      AT91S_SMC_CSR_RWHOLD_0        ;     // 0 Read/Write Hold time required by the sRAM device

Сообщение отредактировал rezident - May 9 2010, 00:06

Причина редактирования: Оформление цитаты исходника.