Я тут файл верхнего уровня привел, так вот ежели в tx_fifo - we зацепить на s_enable (сигнал строба записи фифо от измерителя задержки 500 мкс), то проект не разводится, иначе если we на внешний порт то все собираеться...
кто чего может подсказать, заранее благодарен!!!
CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all;
library UNISIM;
use UNISIM.VComponents.all;
entity MAC_full is
generic (
--####################### -- MAC REGISTERS DECLARATION -- ###############################################
MAC1 : std_logic_vector(15 downto 0):=x"0001"; --MAC Configuration register #1
MAC2 : std_logic_vector(15 downto 0):=x"00b5"; --MAC Configuration register #2
IPGT : std_logic_vector(15 downto 0):=x"0015"; --Back-to-back Inter-packet-Gap register
IPGR : std_logic_vector(15 downto 0):=x"0c12"; --Non-Back-to-back Inter-packet-Gap register
CLRT : std_logic_vector(15 downto 0):=x"370f"; --Collision Window/Retry register
MAXF : std_logic_vector(15 downto 0):=x"0600"; --Maximum Frame register 1536 bytes
SUPP : std_logic_vector(15 downto 0):=x"1100"; --PHY support register
MCFG : std_logic_vector(15 downto 0):=x"0010"; --MII Mgmt Configuration
SA0 : std_logic_vector(15 downto 0):=MAC_addres (47 downto 32); --Station Address
SA1 : std_logic_vector(15 downto 0):=MAC_addres (31 downto 16); --Station Address
SA2 : std_logic_vector(15 downto 0):=MAC_addres (15 downto 0); --Station Address
--#################################################-- ADDITIONAL STATES OF SIGNALS -- ###################
DIVREF_cond : std_logic:='0'; --Divide reference clock
THDF_cond : std_logic:='0'; --Transmit half-duplex flow control
TPCF_cond : std_logic:='0'; --Transmit PAUSE control frame
PPADEN_cond : std_logic:='0'; --Per-packet pad enable
PCRCEN_cond : std_logic:='0'; --Per-packet CRC enable
PHUGEN_cond : std_logic:='0'; --Per-packet huge enable
OVERR_cond : std_logic:='0'; --Per-packet over ride
TXCENI_cond : std_logic:='1'; --Transmit clock enable
RXCENI_cond : std_logic:='1'; --Receive clock enable
TPUR_cond : std_logic:='0';
--#################################################-- CONDITIONS FOR WRITE FIFO --#######################
write_width_tx : integer range 0 to 2048:=32;
write_depth_tx : integer range 0 to 2048:=360;
write_addr_bus_w_tx : integer range 0 to 16:=9;
read_addr_bus_r_tx : integer range 0 to 16:=11;
read_width_tx : integer range 0 to 2048:=8;
--#################################################-- CONDITIONS FOR READ FIFO -- #######################
write_width_rx : integer range 0 to 2048:=8;
write_depth_rx : integer range 0 to 2048:=360*4;
write_addr_bus_w_rx : integer range 0 to 16:=11;
read_addr_bus_r_rx : integer range 0 to 16:=9;
read_width_rx : integer range 0 to 2048:=32;
start_pause : integer range 0 to 256:=5
);
port (
emp,fill_rst : out std_logic;
nRST,p_full : out std_logic;
for_counter : out std_logic;
---##################### -- GLOBAL PORTS -- ####################################
MF100_MHz : in std_logic; -- Global clock for system
reset : in std_logic; -- Global reset
data_is_valid : out std_logic; -- Data is ready for transmiting to the tcp/ip
countData : out std_logic_vector(8 downto 0); -- Number of data which were reading
retry : out std_logic; -- Collision has been detected
rx_rd_clk : in std_logic;
fifo_rst_tx : in std_logic; -- Reset of transmit fifo
--tx_wr_en : in std_logic; -- Transmit fifo write enable
rx_rd_en : in std_logic; -- Receive fifo read enable
rx_dout : out std_logic_VECTOR(read_width_rx-1 downto 0); -- Receive fifo output port
--###################### -- SMII INTERFACE INTERFACE -- ########################
MDC : out std_logic; -- Managment data clock
MDO : out std_logic; -- Managment inout port
MDOEN : out std_logic; -- Managment data enable
--###################### -- MII TRANSMIT INTERFACE -- ##########################
tx_clk : in std_logic; -- Transfer data clock
MTXD : out std_logic_vector(3 downto 0); -- Transmit data vector
MTXEN : out std_logic; -- Transmit enable
MTXER : out std_logic; -- Transmit error
MCRS : in std_logic; -- Carrier sense
MCOL : in std_logic; -- Collision detect
--##################### -- MII RECEIVE INTERFACE -- ##########################
rx_clk : in std_logic; -- Receive data clock
MRXD : in std_logic_vector(3 downto 0); -- Receive data vector
MRXDV : in std_logic; -- Receive data valid
MRXER : in std_logic; -- Receive error
--#################### -- INTERFACE MODULE INTERFACE -- ######################
NOCFR : out std_logic; -- No cipher
DLFCT : out std_logic; -- Disable link fail counter
FRCQ : out std_logic; -- Force quite
ENJAB : out std_logic; -- Enable jaber protection
PHYMOD : out std_logic; -- PHY mode
SPEED : out std_logic; -- Speed selection
SSRR : in std_logic_vector(4 downto 0); -- SMII Status Read register
TSVP_m : out std_logic;
TSV_m : out std_logic_vector(51 downto 0);
RSVP_m : out std_logic;
RSV_m : out std_logic_vector(30 downto 0)
);
end MAC_full;
architecture Behavioral of MAC_full is
component Interface_manager is
generic (
--####################### -- MAC REGISTERS DECLARATION -- ###############################################
MAC1_man : std_logic_vector(15 downto 0); --MAC Configuration register #1
MAC2_man : std_logic_vector(15 downto 0); --MAC Configuration register #2
IPGT_man : std_logic_vector(15 downto 0); --Back-to-back Inter-packet-Gap register
IPGR_man : std_logic_vector(15 downto 0); --Non-Back-to-back Inter-packet-Gap register
CLRT_man : std_logic_vector(15 downto 0); --Collision Window/Retry register
MAXF_man : std_logic_vector(15 downto 0); --Maximum Frame register 1536 bytes
SUPP_man : std_logic_vector(15 downto 0); --PHY Support register (SMII/RMII/PMD/ENDEC)
MCFG_man : std_logic_vector(15 downto 0); --MII Mgmt Configuration
SA0_man : std_logic_vector(15 downto 0); --Station Address
SA1_man : std_logic_vector(15 downto 0); --Station Address
SA2_man : std_logic_vector(15 downto 0) --Station Address
);
port (
Retry_man : out std_logic;
data_received : out std_logic;
--####################### -- TX-interface declaration -- ################################
tx_int_clk_man : in std_logic;
tx_rst_man : in std_logic;
TPD_man : out std_logic_vector(7 downto 0);
TPSF_man : out std_logic;
TPEF_man : out std_logic;
TPUD_man : in std_logic;
TPRT_man : in std_logic;
TPAB_man : in std_logic;
--###################### -- RX-interface declaration -- ##################################
rx_int_clk_man : in std_logic;
rx_rst_man : in std_logic;
RPD_man : in std_logic_vector(7 downto 0);
RPDV_man : in std_logic;
RPSF_man : in std_logic;
RPEF_man : in std_logic;
PCRF_man : in std_logic;
--##################### -- Host interface declaration -- ##################################
host_clk_man : in std_logic;
host_rst_man : in std_logic;
HSTRST_man : out std_logic;
RSTBP_man : out std_logic;
HSTCSN_man : out std_logic;
HSTWRN_man : out std_logic;
HSTADX_man : out std_logic_vector(7 downto 0);
HSTIDAT_man : out std_logic_vector(15 downto 0);
HSTOE_man : in std_logic;
HSTODAT_man : in std_logic_vector(15 downto 0);
RRST_man : in std_logic;
TRST_man : in std_logic;
-- #################### -- Declaration of receive fifo ports -- ###########################
din_re : out std_logic_vector (7 downto 0);
rst_re : out std_logic;-- RX_FIFO reset pin
wr_en_re : out std_logic;
-- ################### -- Declaration of transmit fifo ports -- ###########################
rd_en_tr : out std_logic;
almost_empty_tr : in std_logic;
valid_tr : in std_logic;
dout_tr : in std_logic_vector (7 downto 0);
full_tr : in std_logic;
empty_tr : in std_logic
);
end component Interface_manager;
component counter_fill is
port(
clk : in std_logic;
ena : in std_logic;
reset : in std_logic;
data : out std_logic_vector(31 downto 0)
);
end component;
component time_delimiter is
port(
clk : in std_logic;
rst : in std_logic;
enable : out std_logic;
full : in std_logic
);
end component;
component fifo is
generic(
write_width : integer;
write_depth : integer;
write_addr_bus_w : integer;
read_addr_bus_r : integer;
read_width : integer
);
port(
w_clk,r_clk,rst,we,re,w180_clk : in std_logic;
valid,underflow,empty,full,overflow,almost_empty : out std_logic;
write_count,read_count : out std_logic_vector(23 downto 0);
write_data : in std_logic_vector(write_width-1 downto 0);
read_data : out std_logic_vector(read_width-1 downto 0)
);
end component fifo;
component pe_macmii is
port(
pre_ref,ref_clk,divref,tx_clk,rx_clk,mtxci,txcen,txceni,mrxci,rxcen,rxceni,crs,c
ol,mdi : in std_logic;
tpd : in std_logic_vector(7 downto 0);
tpsf,tpef,tpur,tpcf : in std_logic;
tptv : in std_logic_vector(15 downto 0);
thdf,rx_dv : in std_logic;
rxd : in std_logic_vector(3 downto 0);
rx_er,ppaden,pcrcen,phugen,overr,hstclk, hstrst, hstwrn, hstcsn : in std_logic;
hstadx : in std_logic_vector(7 downto 0);
hstidat : in std_logic_vector(15 downto 0);
ssrr : in std_logic_vector(4 downto 0);
rstbp : in std_logic;
mtxco,txceno,mrxco,rxceno,tx_en : out std_logic;
txd : out std_logic_vector(3 downto 0);
tx_er,mdc,mdo,mdoen,tpud,tpdn,tprt,tpab,tsvp : out std_logic;
tsv : out std_logic_vector(51 downto 0);
txcf,srxen : out std_logic;
rpd : out std_logic_vector(7 downto 0);
rpdv,rpsf,rpef,rsvp : out std_logic;
rsv : out std_logic_vector(30 downto 0);
pcrf : out std_logic;
crco : out std_logic_vector(8 downto 0);
crcg,bco,mco,ucad : out std_logic;
hstodat : out std_logic_vector(15 downto 0);
hstoe,nocfr,dlfct,frcq,enjab,speed,phymod,srstint_ref,srstint_tx,srstint_rx,trst
,rrst : out std_logic
);
end component pe_macmii;
component clk_and_reset_mod is
generic (skip_cycles : integer range 0 to 256);
port(
host_int_clk,tx_int_clk,rx_int_clk,mod_reset : in std_logic;
host_rst,tx_rst,rx_rst,fifo_start_rst : out std_logic;
tx_fifo_rd_clk,rx_fifo_wr_clk,MTXCI,MRXCI,HSTCLK : out std_logic;
F100_MHz,F100MHz_PS,F125MHz_PS : out std_logic
);
end component clk_and_reset_mod;
signal s_host_rst,s_tx_rst,s_rx_rst : std_logic;
signal s_fifo_start_rst : std_logic;
signal s_tx_fifo_rd_clk : std_logic;
signal s_rx_fifo_wr_clk : std_logic;
signal valid_tx : std_logic;
signal rd_en_tx : std_logic;
signal wr_en_rx : std_logic;
signal dout_tx : std_logic_VECTOR(read_width_tx-1 downto 0);
signal din_rx : std_logic_VECTOR(write_width_rx-1 downto 0);
signal s_empty : std_logic;
signal full_tx : std_logic;
signal almost_empty_tx : std_logic;
signal s_TPD : std_logic_vector(7 downto 0);
signal s_TPSF : std_logic;
signal s_TPEF : std_logic;
signal s_TPUD : std_logic;
signal s_TPDN : std_logic;
signal s_TPRT : std_logic;
signal s_TPAB : std_logic;
signal s_RPD : std_logic_vector(7 downto 0);
signal s_RPDV : std_logic;
signal s_RPSF : std_logic;
signal s_RPEF : std_logic;
signal s_PCRF : std_logic;
signal s_HSTRST : std_logic;
signal s_HSTCLK : std_logic;
signal s_HSTCSN : std_logic;
signal s_HSTWRN : std_logic;
signal s_HSTADX : std_logic_vector(7 downto 0);
signal s_HSTIDAT : std_logic_vector(15 downto 0);
signal s_HSTOE : std_logic;
signal s_HSTODAT : std_logic_vector(15 downto 0);
signal s_RRST : std_logic;
signal s_TRST : std_logic;
signal s_MTXCI : std_logic;
signal s_MRXCI : std_logic;
signal s_F100_MHz,s_F100MHz_PS : std_logic;
signal s_crco : std_logic_vector(8 downto 0);
signal s_crcg,s_bco : std_logic;
signal s_mco,s_ucad : std_logic;
signal s_tx_fifo_rst,s_rx_fifo_rst : std_logic;
signal fifo_rst_rx,s_F125MHz_PS : std_logic;
signal read_data_to_buf : std_logic_VECTOR(read_width_rx-1 downto 0);
signal s_enable,tx_wr_en : std_logic;
signal tx_din : std_logic_VECTOR(write_width_tx-1 downto 0); -- Input port of transmit fifo
begin
--p_full<=full_tx ;
s_tx_fifo_rst<=(fifo_rst_tx or s_fifo_start_rst);
s_rx_fifo_rst<=(fifo_rst_rx or s_fifo_start_rst);
nRST<=(not reset);
--p_full<=full_tx;
--fill_rst<=s_tx_fifo_rst;
--for_counter<=s_F100_MHz ;
U1:Interface_manager
generic map (
MAC1,MAC2,IPGT,IPGR,CLRT,MAXF,SUPP,MCFG,SA0,SA1,SA2
)
port map (
Retry_man=>retry,data_received=>data_is_valid,TPD_man=>s_TPD,TPSF_man=>s_TPSF,TPEF_man=>s_TPEF,TPUD_man=>s_TPUD,TPRT_man=>s_TPRT,TPAB_man=>s_TPAB,
RPD_man=>s_RPD,RPDV_man=>s_RPDV,RPSF_man=>s_RPSF,RPEF_man=>s_RPEF,PCRF_man=>s_PCRF,HSTRST_man=>s_HSTRST,HSTCSN_man=>s_HSTCSN,HSTWRN_man=>s_HSTWRN,
HSTADX_man=>s_HSTADX,HSTIDAT_man=>s_HSTIDAT,HSTOE_man=>s_HSTOE,HSTODAT_man=>s_HSTODAT,RRST_man=>s_RRST,TRST_man=>s_TRST,din_re=>din_rx,rst_re=>fifo_rst_rx,
wr_en_re=>wr_en_rx,rd_en_tr=>rd_en_tx,almost_empty_tr=>almost_empty_tx,valid_tr=>valid_tx,dout_tr=>dout_tx,full_tr=>full_tx,empty_tr=>s_empty,
tx_int_clk_man=>s_MTXCI,tx_rst_man=>s_tx_rst,rx_int_clk_man=>s_MRXCI,rx_rst_man=>s_rx_rst,host_clk_man=>s_HSTCLK,host_rst_man=>s_host_rst
);
U2:pe_macmii
port map (
pre_ref=>tx_clk,ref_clk=>tx_clk,divref=>DIVREF_cond,tx_clk=>tx_clk,rx_clk=>rx_clk,mtxci=>s_MTXCI,txcen=>TXCENI_cond,txceni=>TXCENI_cond,mrxci=>s_MRXCI,
rxcen=>RXCENI_cond,rxceni=>RXCENI_cond,crs=>MCRS,col=>MCOL,mdi=>'0',tpd=>s_TPD,tpsf=>s_TPSF,tpef=>s_TPEF, tptv=>x"0000",tpur=>TPUR_cond,tpcf=>TPCF_cond,--tptv=>TPTV_m,
thdf=>THDF_cond,rx_dv=>MRXDV,rxd=>MRXD,rx_er=>MRXER,ppaden=>PPADEN_cond,pcrcen=>PCRCEN_cond,phugen=>PHUGEN_cond,overr=>OVERR_cond,hstclk=>s_HSTCLK,hstrst=>s_HSTRST,
hstwrn=>s_HSTWRN,hstcsn=>s_HSTCSN,hstadx=>s_HSTADX,hstidat=>s_HSTIDAT,ssrr=>SSRR,tx_en=>MTXEN,txd=>MTXD,tx_er=>MTXER,mdc=>MDC,mdo=>MDO,mdoen=>MDOEN,
rstbp=>reset,tpud=>s_TPUD,tpdn=>s_TPDN,tprt=>s_TPRT,tpab=>s_TPAB,tsvp=>TSVP_m,tsv=>TSV_m,rpd=>s_RPD,rpdv=>s_RPDV,rpsf=>s_RPSF,rpef=>s_RPEF,rsvp=>RSVP_m,
rsv=>rsv_m,pcrf=>s_PCRF,crco=>s_crco,crcg=>s_crcg,bco=>s_bco,mco=>s_mco,ucad=>s_ucad,hstodat=>s_HSTODAT,hstoe=>s_HSTOE,nocfr=>NOCFR,dlfct=>DLFCT,frcq=>FRCQ,
enjab=>ENJAB,speed=>SPEED,phymod=>PHYMOD,--srstint_ref,srstint_tx,srstint_rx,
trst=>s_TRST,rrst=>s_RRST
);
U3_tx_fifo:fifo
generic map (write_width_tx,write_depth_tx,write_addr_bus_w_tx,read_addr_bus_r_tx,read_width
_tx)
port map(
w_clk=>s_F100_MHz,w180_clk=>s_F100MHz_PS,r_clk=>s_tx_fifo_rd_clk,rst=>s_tx_fifo_rst,we=>tx_wr_en,re=>rd_en_tx,valid=>valid_tx,almost_empty=>almost_empty_tx,
full=>full_tx,empty=>s_empty,--write_count=>,read_count=>,
write_data=>tx_din,read_data=>dout_tx
);
U4_rx_fifo:fifo
generic map (write_width_rx,write_depth_rx,write_addr_bus_w_rx,read_addr_bus_r_rx,read_width
_rx)
port map(
w_clk=>s_rx_fifo_wr_clk,w180_clk=>s_F125MHz_PS,r_clk=>rx_rd_clk,rst=>s_rx_fifo_rst,we=>wr_en_rx,re=>rx_rd_en,--valid=>valid_tx,
--empty=>empty_tx,full=>full_tx,--write_count=>,read_count=>,
write_data=>din_rx,read_data=>read_data_to_buf
);
U5_clk_rst_block:clk_and_reset_mod
generic map(start_pause)
port map (
host_int_clk=>MF100_MHz,tx_int_clk=>tx_clk,rx_int_clk=>rx_clk,mod_reset=>reset,host_rst=>s_host_rst,tx_rst=>s_tx_rst,rx_rst=>s_rx_rst,
fifo_start_rst=>s_fifo_start_rst,tx_fifo_rd_clk=>s_tx_fifo_rd_clk,rx_fifo_wr_clk=>s_rx_fifo_wr_clk,MTXCI=>s_MTXCI,MRXCI=>s_MRXCI,HSTCLK=>s_HSTCLK,
F100_MHz=>s_F100_MHz,F100MHz_PS=>s_F100MHz_PS,F125MHz_PS=>s_F125MHz_PS
);
U6_buffer_array:
for i in (read_width_rx-1) downto 0 generate
Buffer_Array: OBUF port map (I=>read_data_to_buf(i),O=>rx_dout(i));
end generate;
U7:time_delimiter
port map(
clk=>s_F100_MHz,rst=>reset,enable=>s_enable,full=>full_tx
);
U8:counter_fill
port map(clk=>s_F100_MHz,ena=>s_enable,reset=>s_tx_fifo_rst,data=>tx_din
);
end Behavioral;