Цитата(Andy Mozzhevilov @ Mar 5 2011, 10:16)

For register access, two different modes have to be
distinguished:
· Reset mode
· Operating mode.
The reset mode (see Table 3, control register, bit Reset
Request) is entered automatically after a hardware reset
or when the controller enters the bus-off state (see
Table 5, status register, bit Bus Status). The operating
mode is activated by resetting of the reset request bit in the
control register
When the transmit error counter exceeds the limit of 255 [the bus status bit is set to logic 1 (bus-off)] the
CAN controller will set the reset request bit to logic 1 (present) and an error interrupt is generated, if enabled. It will
stay in this mode until the CPU clears the reset request bit. Once this is completed the CAN controller will wait the
minimum protocol-defined time (128 occurrences of the bus-free signal). After that the bus status bit is cleared
(bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error interrupt is generated, if
enabled.
Да счетчик ошибок увеличивается и когда доходит до 255 чип вырубается и потом никак его не реанимировать, сам он не запускается.