Код
module div_3
(
clk,
q1,
q2,
q3
)
input clk;
output q1;
output q2;
output q3;
reg q1;
reg q2;
reg q3;
reg [1:0] count;
always @(posedge clk)
begin
if(count == 2)
count <= 0;
else
count <= count + 1;
case(count)
0: {q1, q2, q3} <= 3'b001;
1: {q1, q2, q3} <= 3'b010;
2: {q1, q2, q3} <= 3'b100;
end
endmodule
как-то так?