Инициализация PowerPC в Virtex 4-FX Опции

[D-Luxe]

Проблема следующая : не запускается процессор PowerPC, причем до того как забил кристалл еще на 5% все работало.

Есть идея, что Reset неправильно подается. Есть такой компонент proc_sys_reset, у которого есть вход Ext_Reset_In, как на него сброс подавать тоже вопрос.

А может и не в ресете дело.

Не могу разобраться в чем причина.

[maugli]

Вот, что написано в UG018 (v2.4) January 11, 2010 p.171

Timing Specification for Fixed Latency (Virtex-4 and Virtex-II Pro)

The single-cycle and multi-cycle operation modes are designed to guarantee a certain
performance level by the OCM controllers, assuming a certain processor frequency and
quantity of block RAMs. As additional block RAMs are added to a design, the processor
clock frequency must be reduced or wait states must be added in the processor block to
insure that the OCM interface operates correctly. When the processor and OCM controller
clocks operate at integer multiples of each other, wait cycles are automatically added
inside the processor block. The processor core and OCM controllers must be aligned on
rising edges of their respective clocks.

The frequency of the OCM to block RAM interface is determined by running the design
through the Xilinx design implementation tools and performing timing analysis on the
interface. The interface timing is dependent upon the block RAM organization, signal
routing delays, signal loading, block RAM memory access time, clock to output times, and
setup and hold times of the block RAM and processor blocks. Users may need to go
through multiple iterations of evaluating OCM block RAM size versus OCM clock
frequency in order to achieve the optimum performance.

[D-Luxe]

Вот, что написано в UG018 (v2.4) January 11, 2010 p.171

Timing Specification for Fixed Latency (Virtex-4 and Virtex-II Pro)

The single-cycle and multi-cycle operation modes are designed to guarantee a certain
performance level by the OCM controllers, assuming a certain processor frequency and
quantity of block RAMs. As additional block RAMs are added to a design, the processor
clock frequency must be reduced or wait states must be added in the processor block to
insure that the OCM interface operates correctly. When the processor and OCM controller
clocks operate at integer multiples of each other, wait cycles are automatically added
inside the processor block. The processor core and OCM controllers must be aligned on
rising edges of their respective clocks.

The frequency of the OCM to block RAM interface is determined by running the design
through the Xilinx design implementation tools and performing timing analysis on the
interface. The interface timing is dependent upon the block RAM organization, signal
routing delays, signal loading, block RAM memory access time, clock to output times, and
setup and hold times of the block RAM and processor blocks. Users may need to go
through multiple iterations of evaluating OCM block RAM size versus OCM clock
frequency in order to achieve the optimum performance.

И как это связано с Reset circuit и инициализацией проца ?

А по вопросу, есть же XPS, специально GUI сделали, что бы тыкать и читать,
что куда подавать.

XPS ? При создании дифолтного проекта на RST clock_generator - net_gnd, ext_reset_in proc_sys_reset - ресет с кнопки либо net_gnd. С такими настройками работал год, все было шикарно.

После того как начал забивать кристалл начались проблемы с инициализацией PowerPC, поэтому и начал копать. XPS тут уже не помощник.